Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-11430779-B2
Application number	US-202017028855-A
Country	US
Kind code	B2
Filing date	Sep 22, 2020
Priority date	Nov 4, 2019
Publication date	Aug 30, 2022
Grant date	Aug 30, 2022

Abstract

Disclosed are a semiconductor device and a method of fabricating the same. The method includes placing a standard cell, resizing a power via pattern in such a way that the power via pattern has a different width from a width of other via pattern, and applying different design rules to the power via pattern and the other via pattern, respectively, to perform a routing operation on the standard cell.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
placing a standard cell, wherein the standard cell comprises:
a first lower interconnection pattern, a second lower interconnection pattern, and a lower power pattern;
a first upper interconnection pattern, a second upper interconnection pattern, and an upper power pattern;
a first via pattern between the first lower interconnection pattern and the first upper interconnection pattern;
a second via pattern between the second lower interconnection pattern and the second upper interconnection pattern, wherein a width of the second via pattern is larger than a width of the first via pattern; and
a third via pattern between the lower power pattern and the upper power pattern, wherein a first width of the third via pattern and the width of the second via pattern are the same,

resizing the third via pattern to have a second width different from the width of the second via pattern; and
applying different design rules to the second via pattern and the third via pattern, respectively, to perform a routing operation on the standard cell.

2. The method of claim 1 , further comprising restoring a size and shape of the third via pattern to its original size and shape if a result of the routing operation on the standard cell satisfies a design rule for the third via pattern, wherein the original size and shape of the third via pattern is the same as a size and shape of the second via pattern.

3. The method of claim 1 , wherein the second width of the third via pattern is larger than the width of the second via pattern.

4. The method of claim 1 , wherein the second width of the third via pattern is smaller than the width of the second via pattern.

5. The method of claim 1 , wherein the performing of the routing operation on the standard cell comprises:
placing a routing line pattern connecting the standard cell to another standard cell; and
placing a fourth via pattern between the second lower interconnection pattern and the routing line pattern.

6. The method of claim 5 , further comprising checking design rules on geometrical features between the fourth via pattern and the second via pattern and between the fourth via pattern and the third via pattern.

7. The method of claim 6 , wherein a minimum distance between the fourth via pattern and the third via pattern is larger than a minimum distance between the fourth via pattern and the second via pattern.

8. The method of claim 1 , further comprising placing gate patterns and the upper power pattern, before the placing of the standard cell,
wherein the standard cell is placed on the gate patterns and the upper power pattern so as to overlap the gate patterns and the upper power pattern.

9. The method of claim 1 , wherein a line width of the second upper interconnection pattern is larger than a line width of the first upper interconnection pattern, and
wherein a line width of the upper power pattern is larger than the line width of the first upper interconnection pattern.

10. The method of claim 1 , further comprising:
performing an optical proximity correction on a layout on which the routing operation has been performed;
generating a photomask, based on the layout on which the optical proximity correction has been performed; and
performing a semiconductor fabrication process on a substrate using the photomask.

11. A method of fabricating a semiconductor device, comprising:
placing an upper power pattern;
placing a standard cell on the upper power pattern;
placing a power via pattern between the upper power pattern and a lower power pattern of the standard cell;
resizing the power via pattern to differentiate the power via pattern from another via pattern of the semiconductor device; and
performing a routing operation on the standard cell.

12. The method of claim 11 , further comprising:
performing an optical proximity correction on a layout on which the routing operation has been performed;
generating a photomask, based on the layout on which the optical proximity correction has been performed; and
performing a semiconductor fabrication process on a substrate using the photomask.

13. The method of claim 11 , further comprising restoring a size and shape of the power via pattern to its original size and shape if a result of the routing operation on the standard cell satisfies a design rule for the power via pattern.

14. The method of claim 11 , wherein the resizing of the power via pattern comprises increasing or decreasing a width of the power via pattern.

15. The method of claim 11 , further comprising checking a design rule after the routing operation.

16. A method of fabricating a semiconductor device, comprising:
placing a standard cell, wherein the standard cell comprises:
a first lower interconnection pattern, a second lower interconnection pattern, and a lower power pattern;
a first upper interconnection pattern, a second upper interconnection pattern, and an upper power pattern, wherein a width of each of the lower power pattern and the upper power pattern is larger than a line width of each of the first lower interconnection pattern and the second lower interconnection pattern;
a first via pattern between the first lower interconnection pattern and the first upper interconnection pattern;
a second via pattern between the second lower interconnection pattern and the second upper interconnection pattern, wherein a width of the second via pattern is larger than a width of the first via pattern; and
a third via pattern between the lower power pattern and the upper power pattern, wherein a first width of the third via pattern and the width of the second via pattern are the same.

17. The method of claim 16 , further comprising resizing the third via pattern to have a second width different from the width of the second via pattern.

18. The method of claim 17 , wherein the second width of the third via pattern is larger than the width of the second via pattern.

19. The method of claim 17 , wherein the second width of the third via pattern is smaller than the width of the second via pattern.

20. The method of claim 16 , wherein a line width of the second upper interconnection pattern is larger than a line width of the first upper interconnection pattern, and
wherein a line width of the upper power pattern is larger than the line width of the first upper interconnection pattern.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yang Jaewan
• Kim Wootae
• Kim Hyungock
• Park Sangdo
• Seomun Jun

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title