Pattern-based power-and-ground (PG) routing and via creation

Patent metadata

Field	Value
Publication number	US-10204203-B2
Application number	US-201313849427-A
Country	US
Kind code	B2
Filing date	Mar 22, 2013
Priority date	Dec 31, 2012
Publication date	Feb 12, 2019
Grant date	Feb 12, 2019

Abstract

Systems and techniques for pattern-based power-and-ground (PG) routing and via rule based via creation are described. A pattern for routing PG wires can be received. Next, an instantiation strategy may be received, wherein the instantiation strategy specifies an area of an integrated circuit (IC) design layout where PG wires based on the pattern are to be instantiated and specifies one or more net identifiers that are to be assigned to the instantiated PG wires. The PG wires can be instantiated in the IC design layout based on the pattern and the instantiation strategy. Additionally, a set of via rules can be received, wherein each via rule specifies a type of via that is to be instantiated at an intersection between two PG wires that are in two different metal layers. Next, one or more vias can be instantiated in the IC design layout based on the set of via rules.

First claim

What is claimed is:

1. A method for pattern-based power-and-ground (PG) routing in an integrated circuit (IC) design, the method comprising:
detecting an intersection between a first PG wire in a first metal layer and a second PG wire in a second metal layer in an integrated circuit (IC) design layout;
determining that the first PG wire was created using a first pattern, wherein the first pattern is named using a first identifier;
determining that the second PG wire was created using a second pattern, wherein the second pattern is named using a second identifier;
selecting, by using a computer, a via rule from a set of via rules based on matching the first identifier and the second identifier with pairs of identifiers specified in each via rule, wherein the via rule specifies a count and layout of vias; and
creating one or more vias in the IC design at the intersection between the first PG wire in the first metal layer and the second PG wire in the second metal layer based on the via rule.

2. The method of claim 1 , wherein each pattern is described using a pattern definition language, and wherein each pattern specifies at least a shape, size, or relative location of one or more PG wires.

3. The method of claim 1 , wherein said selecting the via rule further includes, responsive to determining that the first and second identifiers did not match any pairs of identifiers, matching a first pattern type corresponding to the first pattern and a second pattern type corresponding to the second pattern with pairs of pattern types specified in the set of via rules.

4. The method of claim 3 , wherein selecting the via rule further includes, responsive to determining that the first and second pattern types did not match any pairs of pattern types, selecting a default via rule.

5. A non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to perform a method for pattern-based power-and-ground (PG) routing in an integrated circuit (IC) design, the method comprising:
detecting an intersection between a first PG wire in a first metal layer and a second PG wire in a second metal layer in an integrated circuit (IC) design layout;
determining that the first PG wire was created using a first pattern, wherein the first pattern is named using a first identifier;
determining that the second PG wire was created using a second pattern, wherein the second pattern is named using a second identifier;
selecting, by using a computer, a via rule from a set of via rules based on matching the first identifier and the second identifier with pairs of identifiers specified in each via rule, wherein the via rule specifies a count and layout of vias; and
creating one or more vias in the IC design at the intersection between the first PG wire in the first metal layer and the second PG wire in the second metal layer based on the via rule.

6. The non-transitory computer-readable storage medium of claim 5 , wherein each pattern is described using a pattern definition language, and wherein each pattern specifies at least a shape, size, or relative location of one or more PG wires.

7. The non-transitory computer-readable storage medium of claim 5 , wherein said selecting the via rule further includes, responsive to determining that the first and second identifiers did not match any pairs of identifiers, matching a first pattern type corresponding to the first pattern and a second pattern type corresponding to the second pattern with pairs of pattern types specified in the set of via rules.

8. The non-transitory computer-readable storage medium of claim 7 , wherein selecting the via rule further includes, responsive to determining that the first and second pattern types did not match any pairs of pattern types, selecting a default via rule.

9. An apparatus, comprising:
a processor; and
a non-transitory computer-readable storage medium storing instructions that, when executed by the processor, cause the apparatus to perform a method for pattern-based power-and-ground (PG) routing in an integrated circuit (IC) design, the method comprising:
detecting an intersection between a first PG wire in a first metal layer and a second PG wire in a second metal layer in an integrated circuit (IC) design layout;
determining that the first PG wire was created using a first pattern, wherein the first pattern is named using a first identifier;
determining that the second PG wire was created using a second pattern, wherein the second pattern is named using a second identifier;
selecting, by using a computer, a via rule from a set of via rules based on matching the first identifier and the second identifier with pairs of identifiers specified in each via rule, wherein the via rule specifies a count and layout of vias; and
creating one or more vias in the IC design at the intersection between the first PG wire in the first metal layer and the second PG wire in the second metal layer based on the via rule.

10. The apparatus of claim 9 , wherein each pattern is described using a pattern definition language, and wherein each pattern specifies at least a shape, size, or relative location of one or more PG wires.

11. The apparatus of claim 9 , wherein said selecting the via rule further includes, responsive to determining that the first and second identifiers did not match any pairs of identifiers, matching a first pattern type corresponding to the first pattern and a second pattern type corresponding to the second pattern with pairs of pattern types specified in the set of via rules.

12. The apparatus of claim 11 , wherein selecting the via rule further includes, responsive to determining that the first and second pattern types did not match any pairs of pattern types, selecting a default via rule.

Assignees

• Synopsys Inc

Inventors

• Lin Yan
• Jiang Yi-Min
• Tai Phillip H
• Yuan Lin

Classifications

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title

• G06F17/5077 Primary

  Physics · mapped topic