Method of generating techfile having reduced corner variation value

Patent metadata

Field	Value
Publication number	US-9477803-B2
Application number	US-201414446752-A
Country	US
Kind code	B2
Filing date	Jul 30, 2014
Priority date	Jul 30, 2014
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

A method of generating a techfile corresponding to a predetermined fabrication process is disclosed. The method includes determining a typical value and a corner variation value usable to model an electrical characteristic of a layer of back end of line (BEOL) features to be fabricated by the predetermined fabrication process, based on measurement of one or more sample integrated circuit chips fabricated by the predetermined fabrication process. A reduced variation value is calculated based on the corner variation value and a scaling factor. The techfile is generated based on the typical value and the reduced variation value.

First claim

What is claimed is:

1. A method of generating a techfile corresponding to a predetermined fabrication process, the method comprising:
determining a typical value and a corner variation value usable to model an electrical characteristic of a layer of back end of line (BEOL) features to be fabricated by the predetermined fabrication process, based on measurement of the electrical characteristic from one or more sample integrated circuit chips fabricated by the predetermined fabrication process;
calculating a reduced variation value by applying a scaling factor to the corner variation value; and
generating, using a processor, the techfile based on the typical value and the reduced variation value,
wherein the techfile is provided for generating a layout design for fabricating additional integrated circuit chips by the predetermined fabrication process.

2. The method of claim 1 , wherein
the layer of BEOL features to be fabricated by the predetermined fabrication process corresponds to an i-th layer of via plugs from a bottom of the BEOL features, an order index i being a positive integer; and
the scaling factor is set as

1

i

.

3. The method of claim 1 , wherein
the layer of BEOL features to be fabricated by the predetermined fabrication process corresponds to a layer of conductive lines; and
the scaling factor is set as a predetermined value ranging from 0.2 to 1.0.

4. The method of claim 3 , wherein the predetermined value ranges from 0.3 to 0.5.

5. The method of claim 1 , further comprising:
determining another typical value and another corner variation value usable to model the electrical characteristic of another layer of BEOL features to be fabricated by the predetermined fabrication process, based on the measurement of the electrical characteristic from the one or more sample integrated circuit chips fabricated by the predetermined fabrication process; and
calculating another reduced variation value based on the another corner variation value and another scaling factor;
wherein
the generating the techfile is performed based on the typical value, the reduced variation value, the another typical value, and the another reduced variation value;
the layer of BEOL features to be fabricated by the predetermined fabrication process corresponds to a layer of via plugs; and
the another layer of BEOL features to be fabricated by the predetermined fabrication process corresponds to a layer of conductive lines.

6. The method of claim 1 , further comprising:
determining another typical value and another corner variation value usable to model the electrical characteristic of another layer of BEOL features to be fabricated by the predetermined fabrication process, based on the measurement of the electrical characteristic from the one or more sample integrated circuit chips fabricated by the predetermined fabrication process; and
calculating another reduced variation value based on the another corner variation value and another scaling factor;
wherein
the generating the techfile is performed based on the typical value, the reduced variation value, the another typical value, and the another reduced variation value;
the layer of BEOL features to be fabricated by the predetermined fabrication process corresponds to a first layer of via plugs;
the another layer of BEOL features to be fabricated by the predetermined fabrication process corresponds to a second layer of via plugs over the first layer of via plugs; and
the another scaling factor is greater than the scaling factor.

7. The method of claim 1 , wherein the electrical characteristic is resistance of the layer of the BEOL features, and the typical value is a unit resistance value.

8. The method of claim 1 , wherein the electrical characteristic is capacitance of the layer of the BEOL features, and the typical value is a unit capacitance value.

9. A method of generating a techfile corresponding to a predetermined fabrication process, the method comprising:
determining a first set of typical values and a first set of corner variation values usable to model an electrical characteristic of a plurality of via plug layers of back end of line (BEOL) features to be fabricated by the predetermined fabrication process, based on measurement of the electrical characteristic from one or more sample integrated circuit chips fabricated by the predetermined fabrication process;
calculating a first set of reduced variation values based on multiplying the first set of corner variation values by a corresponding one of a first set of scaling factors, a first scaling factor of the first set of scaling factors of an upper layer of the plurality of via plug layers being less than a second scaling factor of the first set of scaling factors of a lower layer of the plurality of via plug layers; and
generating, using a processor, the techfile based on the typical values and the reduced variation values,
wherein the techfile is provided for generating a layout design for fabricating additional integrated circuit chips by the predetermined fabrication process.

10. The method of claim 9 , wherein a scaling factor of the scaling factors corresponding to an i-th layer of via plugs from a bottom of all BEOL features is

1

i

.

11. The method of claim 9 , further comprising:
determining a second set of typical values and a second set of corner variation values usable to model the electrical characteristic of a plurality of conductive line layers of the BEOL features to be fabricated by the predetermined fabrication process, based on the measurement of the electrical characteristic from the one or more sample integrated circuit chips fabricated by the predetermined fabrication process; and
calculating a second set of reduced variation values based on multiplying the second set of corner variation values by another scaling factor;
wherein the generating the techfile is performed based on the first set of typical values, the first set of reduced variation values, the second set of typical values, and the second set of reduced variation values.

12. The method of claim 11 , wherein the predetermined scaling factor is set as a predetermined value ranging from 0.2 to 1.0.

13. The method of claim 12 , wherein the predetermined value ranges from 0.3 to 0.5.

14. The method of claim 11 , further comprising:
generating another techfile based on the first set of typical values, the second set of typical values, the first set of corner variation values, and the second set of corner variation values.

15. The method of claim 9 , wherein the electrical characteristic is resistance of the layer of the BEOL features, and the first set of typical values is a set of unit resistance values.

16. The method of claim 9 , wherein the electrical characteristic is capacitance of the layer of the BEOL features, and the first set of typical values is a set of unit capacitance values.

17. A system for generating a techfile corresponding to a predetermined fabrication process, the system comprising:
a processor;
a non-transitory, computer readable storage medium configured to store executable instructions, the executable instructions configured to cause t

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Chung-Hsing
• Tam King-Ho
• Chen Yen-Pin
• Chen Wen-Hao
• Lin Chung-Kai
• Yao Chih-Hsiang

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F30/367 Primary

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F17/5009

  Physics · mapped topic

• G06F17/5081 Primary

  Physics · mapped topic