Credit aware central arbitration for multi-endpoint, multi-core system

Patent metadata

Field	Value
Publication number	US-11429526-B2
Application number	US-201916653221-A
Country	US
Kind code	B2
Filing date	Oct 15, 2019
Priority date	Oct 15, 2018
Publication date	Aug 30, 2022
Grant date	Aug 30, 2022

Abstract

A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to determine a first destination device connected to the data path and associated with the first memory access request and a first credit threshold corresponding to the first memory access request. The arbiter circuit is further configured to determine a second destination device connected to the data path and associated with the second memory access request and a second credit threshold corresponding to the second memory access request. The arbiter circuit is configured to arbitrate access to the data path by the first memory access request and the second memory access request based on the first credit threshold and the second credit threshold.

First claim

What is claimed is:

1. A device comprising:
a data path;
a cache configuration register;
a first interface configured to receive a first memory access request from a first peripheral device;
a second interface configured to receive a second memory access request from a second peripheral device; and
an arbiter circuit coupled to the cache configuration register, the arbiter circuit configured to:
receive a plurality of memory access requests including the first memory access request and the second memory access request, wherein each of the plurality of memory access requests includes a respective credit threshold;
determine a first destination device connected to the data path and associated with the first memory access request and a first credit threshold corresponding to the first memory access request;
determine a second destination device connected to the data path and associated with the second memory access request and a second credit threshold corresponding to the second memory access request;
determine a winning request by arbitrating access to the data path by the first memory access request and the second memory access request based on a comparison of the first credit threshold to a first number of credits allocated to the first destination device and a comparison of the second credit threshold to a second number of credits allocated to the second destination device, wherein the cache configuration register stores a bit mask indicating a way for the winning request; and
in response to the winning request being the first memory access request:
decrement the first number of credits with the first credit threshold; and
in response to the first number of credits at or below a lower credit threshold for the first destination device, stall selecting the first destination device in subsequent arbitrations until the first number of credits is at or above an upper credit threshold for the first destination device, wherein the upper credit threshold is set to a highest credit threshold of the plurality of memory access requests.

2. The device of claim 1 , wherein the arbiter circuit is configured to drive the first memory access request to the data path in advance of the second memory access request in response to the first number of credits satisfying the first credit threshold and the second number of credits failing to satisfy the second credit threshold.

3. The device of claim 1 , wherein the arbiter circuit is configured to arbitrate access to the data path by the first memory access request and the second memory access request based further on a fair-share algorithm in response to the first number of credits satisfying the first credit threshold and the second number of credits satisfying the second credit threshold.

4. The device of claim 1 , wherein the arbiter circuit is configured to arbitrate access to the data path by the first memory access request and the second memory access request based further on a round robin algorithm in response to the first number of credits satisfying the first credit threshold and the second number of credits satisfying the second credit threshold.

5. The device of claim 1 , wherein the arbiter circuit is configured to arbitrate access to the data path by the first memory access request and the second memory access request based further on a first priority level of the first memory access request and a second priority level of the second memory access request in response to the first number of credits satisfying the first credit threshold and the second number of credits satisfying the second credit threshold.

6. The device of claim 1 , further comprising a starvation register configured to store a starvation threshold associated with the first interface, wherein the arbiter circuit is configured to arbitrate access to the data path by the first memory access request and the second memory access request based further on a comparison of the starvation threshold to a count of cycles the first memory access request has lost arbitration to the starvation threshold in response to the first number of credits satisfying the first credit threshold and the second number of credits satisfying the second credit threshold.

7. The device of claim 6 , further comprising a configuration arbiter circuit connected to the data path and configured to arbitrate access to the starvation register.

8. The device of claim 1 , further comprising:
a memory bank; and
a read-modify-write queue connected to the memory bank and to the data path, the read-modify-write queue configured to arbitrate access to the memory bank.

9. The device of claim 8 , further comprising:
a second memory bank; and
a second read-modify-write queue connected to the second memory bank and to the data path, the second read-modify-write queue configured to arbitrate access to the second memory bank.

10. The device of claim 9 , further comprising:
an external memory interface; and
an external memory arbiter connected to the external memory interface, to the read-modify-write queue, and to the second read-modify-write queue, wherein the read-modify-write queue and the second read-modify-write queue are further configured to arbitrate access to the external memory arbiter, and wherein the external memory arbiter is configured to arbitrate access to the external memory interface.

11. A system comprising:
a first processor package;
a second processor package; and
a multi-core shared memory controller (MSMC) including:
a data path;
a cache configuration register;
a first interface connected to the first processor package and configured to receive a first memory access request from the first processor package;
a second interface connected to the second processor package and configured to receive a second memory access request from the second processor package; and
an arbiter circuit coupled to the cache configuration register, the arbiter circuit configured to:
receive a plurality of memory access requests including the first memory access request and the second memory access request, wherein each of the plurality of memory access requests includes a respective credit threshold;
determine a first destination device associated with the first memory access request and a first credit threshold corresponding to the first memory access request;
determine a second destination device associated with the second memory access request and a second credit threshold corresponding to the second memory access request; and
determine a winning request by arbitrating access to the data path by the first memory access request and the second memory access request based on a comparison of the first credit threshold to a first number of credits allocated to the first destination device and a comparison of the second credit threshold to a second number of credits allocated to the second destination device, wherein the cache configuration register stores a bit mask indicating a way for the winning request; and

in response to the winning request being the first memory access request:
decrement the first number of credits with the first credit threshold; and
in response to the first number of credits at or below a lower credit threshold for the first destination device, stall selecting the first destination device in subsequent arbitrations until the first number of credits is at or above an upper credit threshold for the first destination device, wherein the upper credit threshold is set to a highest credit threshold of the plurality of memory access requests.

12. The system of claim 11 , wherein the arbiter circuit is configured to drive the first memory access request to the da

Assignees

• Texas Instruments Inc

Inventors

• Pierson Matthew David
• Chirca Kai
• Wu Daniel

Classifications

• G06F12/084 Primary

  with a shared cache · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F11/1004 Primary

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F13/1663

  Access to shared memory · CPC title