Reduced thermal resistance attenuator on high-thermal conductivity substrates for quantum applications

US11424522B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11424522-B2
Application numberUS-202016751444-A
CountryUS
Kind codeB2
Filing dateJan 24, 2020
Priority dateFeb 12, 2018
Publication dateAug 23, 2022
Grant dateAug 23, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Techniques for facilitating reduced thermal resistance attenuator on high-thermal conductivity substrates for quantum applications are provided. A device can comprise a substrate that provides a thermal conductivity level that is more than a defined thermal conductivity level. The device can also comprise one or more grooved transmission lines formed in the substrate. The one or more grooved transmission lines can comprise a powder substance. Further, the device can comprise one or more copper heat sinks formed in the substrate. The one or more copper heat sinks can provide a ground connection. Further, the one or more copper heat sinks can be formed adjacent to the one or more grooved transmission lines.

First claim

Opening claim text (preview).

What is claimed is: 1. A device, comprising: a substrate that provides a thermal conductivity level that is more than a defined thermal conductivity level; one or more grooved areas for transmission lines, the one or more grooved areas having a first depth and formed in the substrate, wherein the one or more grooved areas has disposed within at least one transmission line and at least one resistor; one or more heat sinks having a second depth formed in the substrate, wherein the second depth is greater than the first depth; and connections coupling the one or more heat sinks to the at least one resistor, wherein the one or more grooved areas for transmission lines comprise a first powder selected from a group consisting of Nichrome (NiCr), copper, platinum, silver, and brass, and wherein the at least one resistor is comprised of a second powder distinct from the first powder and comprised of Nichrome (NiCr). 2. The device of claim 1 , wherein the thermal conductivity level of the substrate is in a range of around 100 to 200 watts per meter per Kelvin (W/m/K). 3. The device of claim 1 , wherein the substrate comprises a material selected from a group consisting of sapphire, silicon, fused silica, quartz, Magnesium Oxide (MgO), and Gallium Arsenide (GaAs). 4. The device of claim 1 , wherein the one or more grooved areas for transmission lines facilitate thermalization to reduce a metal-substrate interfacial thermal resistance. 5. The device of claim 1 , further comprising a ground plane, wherein the substrate is over the ground plane. 6. The device of claim 1 , wherein the device is a microwave attenuator device that is employed in cryogenic environments. 7. The device of claim 1 , wherein the at least one resistor comprises a resistivity level higher than a defined resistivity level, wherein the one or more heat sinks absorb heat from the at least one resistor. 8. The device of claim 7 , wherein the defined resistivity level is around 100 microhm centimeter. 9. A microwave attenuator device, comprising: a substrate that provides a thermal conductivity level that is more than a defined thermal conductivity level; one or more grooved areas for transmission lines formed in the substrate and having at least one resistor within the one or more grooved areas; and one or more heat sinks having a depth greater than a second depth of the one or more grooved areas and formed in the substrates, wherein the one or more grooved areas for transmission lines comprise a first powder selected from a group consisting of Nichrome (NiCr), copper, platinum, silver, and brass, and wherein the at least one resistor is comprised of a second powder in the one or more grooved areas distinct from the first powder and comprised of Nichrome NiCr. 10. The microwave attenuator device of claim 9 , wherein the substrate comprises a material selected from a group consisting of sapphire, silicon, fused silica, quartz, Magnesium Oxide (MgO), and Gallium Arsenide (GaAs), and wherein the one or more grooved areas for transmission lines comprise the first powder selected from a group consisting of Nichrome (NiCr), copper, platinum, silver, and brass. 11. The microwave attenuator device of claim 9 , wherein the thermal conductivity level of the substrate is in a range of about 100 to 200 watts per meter per Kelvin (W/m/K), wherein the one or more grooved areas for transmission lines facilitate thermalization to reduce a metal-substrate interfacial thermal resistance.

Assignees

Inventors

Classifications

  • H01P1/227Primary

    Strip line attenuators (H01P1/23 takes precedence) · CPC title

  • for compensation of, or protection against, temperature or moisture effects {; for improving power handling capability (H01P1/04, H01P1/08 take precedence)} · CPC title

  • H01P11/003Primary

    Manufacturing lines with conductors on a substrate, e.g. strip lines, slot lines · CPC title

  • Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title

  • Quantum computing, i.e. information processing based on quantum-mechanical phenomena · CPC title

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What does patent US11424522B2 cover?
Techniques for facilitating reduced thermal resistance attenuator on high-thermal conductivity substrates for quantum applications are provided. A device can comprise a substrate that provides a thermal conductivity level that is more than a defined thermal conductivity level. The device can also comprise one or more grooved transmission lines formed in the substrate. The one or more grooved tr…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H01P1/227. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 23 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).