Electronic device bonding structure and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-11424216-B2
Application number	US-202017030380-A
Country	US
Kind code	B2
Filing date	Sep 24, 2020
Priority date	Aug 31, 2020
Publication date	Aug 23, 2022
Grant date	Aug 23, 2022

Abstract

A fabrication method of an electronic device bonding structure includes the following steps. A first electronic component including a first conductive bonding portion is provided. A second electronic component including a second conductive bonding portion is provided. A first organic polymer layer is formed on the first conductive bonding portion. A second organic polymer layer is formed on the second conductive bonding portion. Bonding is performed on the first electronic component and the second electronic component through the first conductive bonding portion and the second conductive bonding portion, such that the first electronic component and the second electronic component are electrically connected. The first organic polymer layer and the second organic polymer layer diffuse into the first conductive bonding portion and the second conductive bonding portion after the bonding. An electronic device bonding structure is also provided.

First claim

What is claimed is:

1. An electronic device bonding structure, comprising:
a first electronic component, comprising a first conductive bonding portion;
a second electronic component, comprising a second conductive bonding portion;
a first organic polymer layer, located on a side wall of the first conductive bonding portion; and
a second organic polymer layer, located on a side wall of the second conductive bonding portion, wherein:
the second conductive bonding portion is bonded to the first conductive bonding portion, such that the first electronic component and the second electronic component are electrically connected, and
dies in the first conductive bonding portion and dies in the second conductive bonding portion have a refinement die distribution structure.

2. The electronic device bonding structure according to claim 1 , wherein the refinement die distribution structure is a structure in which sizes of part of the dies in the first conductive bonding portion and the second conductive bonding portion close to a bonding junction of the first conductive bonding portion and the second conductive bonding portion are less than sizes of part of the dies away from the bonding junction of the first conductive bonding portion and the second conductive bonding portion.

3. The electronic device bonding structure according to claim 1 , wherein the first electronic component and the second electronic component comprise wafer-to-wafer bonding or circuit substrate-to-circuit substrate bonding.

4. The electronic device bonding structure according to claim 1 , wherein the first conductive bonding portion and the second conductive bonding portion respectively are a conductive bump and a conductive pad.

5. The electronic device bonding structure according to claim 1 , wherein a plurality of the first conductive bonding portions and a plurality of the second conductive bonding portions are provided, and a cavity is formed between adjacent first conductive bonding portions and between adjacent second conductive bonding portions.

6. The electronic device bonding structure according to claim 5 , wherein the cavity does not have an underfill.

7. The electronic device bonding structure according to claim 1 , wherein the first conductive bonding portion directly contacts the second conductive bonding portion.

8. The electronic device bonding structure according to claim 1 , wherein:
the first organic polymer layer is further located on a surface of the first electronic component opposite to the first conductive bonding portion; and
the second organic polymer layer is further located on a surface of the second electronic component opposite to the second conductive bonding portion.

Assignees

• Unimicron Technology Corp

Inventors

• Hsu Chia-Fu
• Yang Kai-Ming
• Lin Pu-Ju
• Ko Cheng-Ta

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/314

  characterized by direct bonding of pads or other interconnections · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title