Efficient retention flop utilizing different voltage domain

Patent metadata

Field	Value
Publication number	US-11418174-B2
Application number	US-202117245623-A
Country	US
Kind code	B2
Filing date	Apr 30, 2021
Priority date	Apr 22, 2019
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

A system and method for efficiently retaining data in sequential elements during power down modes. In various embodiments, a master latch of a flip-flop circuit receives an always-on first power supply voltage, whereas, a slave latch and other surrounding circuitry receives a second power supply voltage capable of being powered down. During a power down mode, circuitry consumes less power while the master latch retains stored data. In some designs, the flip-flop circuit is a level shifting circuit, and the always-on first power supply voltage is less than the second power supply voltage. The master latch uses complex gates with a p-type transistor at the top of a stack of p-type transistors receiving the always-on power supply voltage level on its source terminal and the retained data value on its gate terminal. This top p-type transistor is capable of remaining disabled even when used in a level shifting manner.

First claim

What is claimed is:

1. An apparatus comprising:
a first device of a first device type configured to receive, on a first type of terminal, a first power supply voltage;
a second device of the first device type configured to:
receive, on the first type of terminal of the second device, a first voltage level on a second type of terminal of the first device; and
receive, on a third type of terminal of the second device, a data signal based on a second power supply voltage different from the first power supply voltage; and

a third device of the first device type configured to:
receive, on the first type of terminal of the third device, the first voltage level; and
receive, on the third type of terminal of the third device, a clock signal based on the second power supply voltage; and

a first device of a second device type different from the first device type configured to:
receive, on a second type of terminal of the first device of the second device type, a second voltage level on each of the second type of terminals of the second device and the third device; and
receive, on a source terminal, a ground reference level; and

wherein the second voltage level is retained based on the first power supply voltage, in response to detecting that the second power supply voltage transitions to the ground reference level.

2. The apparatus as recited in claim 1 , wherein, based at least in part on a detection that an isolate signal toggles between being asserted and negated:
the first power supply voltage remains at a first positive, non-zero voltage level; and
the second power supply voltage transitions between a ground reference level and a second positive, non-zero voltage level different from the first positive, non-zero voltage level.

3. The apparatus as recited in claim 1 , wherein the apparatus is a master latch of a data retention flip-flop circuit configured to convey the second voltage level as a latch output to a slave latch.

4. The apparatus as recited in claim 1 , wherein the first power supply voltage is less than the second power supply voltage.

5. The apparatus as recited in claim 1 , wherein:
a device is a transistor with a source terminal as the first type of terminal, a drain terminal as the second type of terminal and a gate terminal as the third type of terminal;
the first device type is a p-type device; and
the second device type is an n-type device.

6. The apparatus as recited in claim 5 , wherein the apparatus further comprises a second device of the second device type configured to:
receive, on a drain terminal, the second voltage level;
receive, on a source terminal, the ground reference level; and
convey a third voltage level to gate terminals of each of the first device of the first device type and the first device of the second device type.

7. The apparatus as recited in claim 6 , wherein each of the second device of the first device type, the third device of the first device type and the first device of the second device type is further configured to convey the second voltage level to gate terminals of each of a fourth device of the first device type and the second device of the second device type.

8. A method, comprising:
receiving, by a source terminal of a first p-type device, a first power supply voltage;
conveying, by a drain terminal of the first p-type device, a first voltage level based on the first power supply voltage;
receiving, by a source terminal of a second p-type device, the first voltage level;
receiving, by a gate terminal of the second p-type device, a data signal based on a second power supply voltage different from the first power supply voltage;
receiving, by a source terminal of a third p-type device, the first voltage level;
receiving, by a gate terminal of the third p-type device, a clock signal based on the second power supply voltage;
conveying, by each of the drain terminals of the second p-type device and the third p-type device, a second voltage level;
receiving, by a drain terminal of a first n-type device, the second voltage level;
receiving, by a source terminal of the first n-type device, a ground reference level; and
retaining the second voltage level based on the first power supply voltage, in response to detecting that the second power supply voltage transitions to the ground reference level.

9. The method as recited in claim 8 , wherein, based at least in part on a detection that an isolate signal toggles between being asserted and negated, the method further comprises:
remaining, by the first power supply voltage, at a first positive, non-zero voltage level; and
transitioning, by the second power supply voltage, between a ground reference level and a second positive, non-zero voltage level different from the first positive, non-zero voltage level.

10. The method as recited in claim 8 , further comprising conveying, by a master latch of a data retention flip-flop circuit, the second voltage level as a latch output to a slave latch, wherein the master latch comprises each of the first p-type device, the second p-type device, the third p-type device and the first n-type device.

11. The method as recited in claim 8 , wherein:
a device is a transistor with a source terminal as a first type of terminal, a drain terminal as a second type of terminal and a gate terminal as a third type of terminal;
a first device type is a p-type device; and
a second device type is an n-type device.

12. The method as recited in claim 11 , further comprising:
receiving, by a drain terminal of a second n-type device, the second voltage level;
receiving, by a source terminal of the second n-type device, the ground reference level; and
conveying, by the second n-type device, a third voltage level to gate terminals of each of the first p-type device and the first n-type device.

13. The method as recited in claim 12 , further comprising conveying, by each of the second p-type device, the third p-type device and the first n-type device, the second voltage level to gate terminals of each of a fourth p-type device and the second n-type device.

14. A data retention flip-flop circuit comprising:
a master latch configured to:
receive a first power supply voltage;
receive a data signal based on a second power supply voltage different from the first power supply voltage;
receive a clock signal based on the second power supply voltage; and
convey at least one latch output; and

a slave latch configured to receive the at least one latch output; and
wherein the master latch comprises:
a first device of a first device type configured to receive, on a first type of terminal, a first power supply voltage;
a second device of the first device type configured to:
receive, on the first type of terminal of the second device, a first voltage level on a second type of terminal of the first device; and
receive, on a third type of terminal of the second device, a data signal based on a second power supply voltage different from the first power supply voltage; and

a third device of the first device type configured to:
receive, on the first type of terminal of the third device, the first voltage level; and
receive, on the third type of terminal of the third device, a clock signal based on the second power supply voltage; and

a first device of a second device type different from the first device type configured to:
receive, on a second type of terminal of the first device of the second device type, a second voltage level on each of the second type of terminals of the second device and the third device; and
receive, on a source terminal, a ground reference lev

Assignees

• Apple Inc

Inventors

• Hess Greg M
• Venugopal Vivekanandan
• Zyuban Victor

Classifications

• G11C19/184

  with field-effect transistors, e.g. MOS-FET · CPC title

• G11C7/106

  Data output latches · CPC title

• H03K3/356078

  with synchronous operation · CPC title

• G11C7/1087

  Data input latches · CPC title

• H03K3/35606

  with synchronous operation · CPC title