High speed voltage level shifter

Patent metadata

Field	Value
Publication number	US-9948303-B2
Application number	US-201615367751-A
Country	US
Kind code	B2
Filing date	Dec 2, 2016
Priority date	Jun 30, 2016
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.

First claim

What is claimed is:

1. An interface, comprising:
a voltage level shifter, comprising:
a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain;
a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node;
an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor;
a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground; and
an enable circuit configured to receive an enable signal, to enable the voltage level shifter when the enable signal has a first logic state, and to disable the voltage level shifter when the enable signal has a second logic state; and

a decoder coupled to the enable circuit, wherein the decoder is configured to receive an address signal, and to generate the enable signal based on the address signal.

2. The interface of claim 1 , wherein the inverter is powered by the supply voltage of the second power domain.

3. The interface of claim 1 , wherein the input signal has a voltage range that is at least 20 percent lower than the supply voltage of the second power domain.

4. The interface of claim 1 , wherein the enable signal is in the second power domain.

5. The interface of claim 1 , wherein the enable circuit is configured to pull the node to the supply voltage of the second power domain when the enable signal has the second logic state.

6. The interface of claim 1 , wherein the enable circuit comprises a second NMOS transistor having a gate configured to receive the enable signal, wherein the first and second NMOS transistors are coupled in series between the node and the ground.

7. The interface of claim 6 , wherein the first logic state of the enable signal is a logic one, and the second logic state of the enable signal is a logic zero.

8. The interface of claim 7 , wherein the enable circuit further comprises a third PMOS transistor having a gate configured to receive the enable signal, wherein the third PMOS transistor is coupled between the supply voltage of the second power domain and the node.

9. The interface of claim 1 , wherein the input signal has a first voltage range, the enable signal has a second voltage range, and the second voltage range is at least 20 percent greater than the first voltage range.

10. The interface of claim 1 , wherein the inverter is implemented with a NAND gate.

11. A method for level shifting an input signal from a first power domain to a second power domain using a voltage level shifter, the voltage level shifter comprising first and second p-type metal-oxide-semiconductor (PMOS) transistors coupled in series between a supply voltage of the second power domain and a node, and a first n-type metal-oxide-semiconductor (NMOS) transistor coupled between the node and a ground, the method comprising;
inputting the input signal in the first power domain to a gate of the first PMOS transistor and a gate of the first NMOS transistor;
inverting a signal at the node to obtain an inverted signal;
inputting the inverted signal to a gate of the second PMOS transistor;
generating an enable signal based on an address signal;
enabling the voltage level shifter if the enable signal has a first logic value; and
disabling the voltage level shifter if the enable signal has a second logic value.

12. The method of claim 11 , wherein the inverted signal has a voltage range approximately equal to the supply voltage of the second power domain.

13. The method of claim 11 , wherein the input signal has a voltage range that is at least 20 percent lower than the supply voltage of the second power domain.

14. The method of claim 11 , wherein disabling the voltage level shifter comprises decoupling a source of the first NMOS transistor from the ground.

15. The method of claim 14 , further comprising pulling the node to the supply voltage of the second power domain when the voltage level shifter is disabled.

16. An interface, comprising:
a first buffer in a first power domain; and
voltage level shifter, comprising:
a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal from the first buffer;
a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node;
an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor; and
a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal from the first buffer, wherein the first NMOS transistor is coupled between the node and a ground.

17. The interface of claim 16 , further comprises a second buffer in the second power domain, wherein the output of the inverter of the voltage level shifter is coupled to the second buffer.

18. The interface of claim 16 , wherein the input signal has a voltage range that is at least 20 percent lower than the supply voltage of the second power domain.

19. The interface of claim 16 , further comprising an enable circuit configured to receive an enable signal in the second power domain, to enable the voltage level shifter when the enable signal has a first logic state, and to disable the voltage level shifter when the enable signal has a second logic state.

20. The interface of claim of 19 , wherein the enable circuit comprises a second NMOS transistor having a gate configured to receive the enable signal, wherein the first and second NMOS transistors are coupled in series between the node and the ground.

21. The interface of claim 20 , wherein the first logic state of the enable signal is a logic one, and the second logic state of the enable signal is a logic zero.

22. The interface of claim 21 , wherein the enable circuit further comprises a third PMOS transistor having a gate configured to receive the enable signal, wherein the third PMOS transistor is coupled between the supply voltage of the second power domain and the node.

23. The interface of claim 19 , further comprising a decoder configured to receive an address signal, to set the enable signal to the first logic state if the address signal addresses the first buffer, and to set the enable signal to the second logic state if the address signal does not address the first buffer.

24. The interface of claim 23 , wherein the first buffer comprises a register.

25. The interface of claim 16 , wherein the input signal has a first voltage range, the enable signal has a second voltage range, and the second voltage range is at least 20 percent greater than the first voltage range.

26. The interface of claim 1 , further comprising:
a register coupled to the gate of the first PMOS and the gate of the second NMOS, wherein the decoder is configured to determine whether the register is addressed by the address signal, to set the enable signal to the first logic state if the register is addressed by the address signal, and to set the enable signal to the second logic state if the register is not addressed by the address signal.

27. The interface of claim 6 , further comprising:
a register coupled t

Assignees

• Qualcomm Inc

Inventors

• Narayanan Venkat
• Vattikonda Rakesh
• Lu de
• Vilangudipitchai Ramaprasath
• Sinharoy Samrat
• Chen Rui

Classifications

• H03K19/018521 Primary

  of complementary type, e.g. CMOS · CPC title

• H03K19/0013

  in field effect transistor circuits · CPC title

• H03K19/01855

  synchronous, i.e. using clock signals · CPC title

• H03K3/356121

  with synchronous operation (H03K3/35613, H03K3/356147 take precedence) · CPC title

• H03K19/0963

  using transistors of complementary type (H03K19/0966 takes precedence) · CPC title