Methods to embed magnetic material as first layer on coreless substrates and corresponding structures

Patent metadata

Field	Value
Publication number	US-11417614-B2
Application number	US-201815938114-A
Country	US
Kind code	B2
Filing date	Mar 28, 2018
Priority date	Mar 28, 2018
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

First claim

What is claimed is:

1. An electronic package, comprising:
a first layer, wherein the first layer comprises a dielectric material;
a second layer over the first layer, wherein the second layer comprises a magnetic material having an uppermost surface;
a third layer over the second layer, wherein the third layer comprises a dielectric material, and wherein the third layer entirely covers a first surface of the second layer; and
a first conductive layer and a second conductive layer embedded within the second layer, wherein sidewalls of the first conductive layer and the second conductive layer are substantially vertical, and wherein the first conductive layer and the second conductive layer have an uppermost surface horizontally co-planar with the uppermost surface of the magnetic material of the second layer.

2. The electronic package of claim 1 , wherein the first layer is a photoimageable dielectric (PID).

3. The electronic package of claim 2 , wherein an opening through the first layer exposes a surface of the first conductive layer.

4. The electronic package of claim 1 , wherein the second conductive layer comprises a vertical pillar.

5. The electronic package of claim 1 , further comprising:
a magnetic block formed on a surface of the first layer opposite from the second layer.

6. The electronic package of claim 5 , wherein the first conductive layer comprises a conductive trace between the magnetic block and the second layer.

7. The electronic package of claim 6 , further comprising:
an inductor, wherein the inductor comprises portions of the first conductive layer, the second conductive layer, and the magnetic block, and wherein the inductor is a transmission line inductor, a spiral inductor, or a solenoid inductor.

8. The electronic package of claim 1 , further comprising:
a fourth layer over the third layer, wherein the fourth layer is a dielectric material.

9. The electronic package of claim 8 , further comprising:
a third conductive layer through the third layer;
a fourth conductive layer over the third layer;
a fifth conductive layer in the fourth layer; and
a sixth conductive layer over the fourth layer.

10. The electronic package of claim 9 , further comprising a first solder resist layer over the fourth layer, wherein openings are formed into the solder resist layer to expose portions of the fifth conductive layer.

11. The electronic package of claim 10 , further comprising:
a second solder resist layer over a surface of the first layer opposite the second layer.

12. The electronic package of claim 11 , further comprising:
a conductive layer through the first layer, wherein the second solder resist comprises an opening to expose a portion of the conductive layer.

13. The electronic package of claim 1 , wherein the electronic package is a coreless package.

14. An electronic package, comprising:
a first layer, wherein the first layer comprises a magnetic material having an uppermost surface;
a first conductive layer and a second conductive layer embedded within the first layer, wherein the first conductive layer and the second conductive layer have an uppermost surface horizontally co-planar with the uppermost surface of the magnetic material of the first layer;
a first barrier layer along a bottom surface of the first layer and along sidewall surfaces of the first layer, wherein the first barrier layer separates the first layer from the first conductive layer and the second conductive layer; and
a second barrier layer over a top surface of the first layer.

15. The electronic package of claim 14 , wherein the sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

16. The electronic package of claim 14 , wherein a thickness of the first barrier layer is less than a thickness of the second barrier layer.

17. The electronic package of claim 14 , further comprising:
a third conductive layer through the second barrier layer;
a fourth conductive layer over the second barrier layer;
a buildup layer over the second barrier layer, wherein the buildup layer comprises a dielectric material;
a fifth conductive layer through the buildup layer; and
a sixth conductive layer over the buildup layer.

18. The electronic package of claim 17 , further comprising:
a first solder resist layer over the buildup layer; and
a second solder resist layer contacting a portion of the first barrier layer.

19. The electronic package of claim 18 , further comprising:
a magnetic block formed on through an opening in the second solder resist layer; and
an inductor comprising portions of the first conductive layer, the first layer, and the magnetic block.

20. The electronic package of claim 14 , wherein the electronic package is a coreless package.

21. An electronic package, comprising:
a first layer, wherein the first layer comprises a dielectric material;
a second layer over the first layer, wherein the second layer comprises a magnetic material;
a third layer over the second layer, wherein the third layer comprises a dielectric material, and wherein the third layer entirely covers a first surface of the second layer;
a first conductive layer and a second conductive layer embedded within the second layer, wherein sidewalls of the first conductive layer and the second conductive layer are substantially vertical;
a fourth layer over the third layer, wherein the fourth layer is a dielectric material;
a third conductive layer through the third layer;
a fourth conductive layer over the third layer;
a fifth conductive layer in the fourth layer;
a sixth conductive layer over the fourth layer; and
a first solder resist layer over the fourth layer, wherein openings are formed into the solder resist layer to expose portions of the fifth conductive layer.

22. An electronic package, comprising:
a first layer, wherein the first layer comprises a magnetic material;
a first conductive layer and a second conductive layer embedded within the first layer;
a first barrier layer along a bottom surface of the first layer and along sidewall surfaces of the first layer, wherein the first barrier layer separates the first layer from the first conductive layer and the second conductive layer;
a second barrier layer over a top surface of the first layer;
a third conductive layer through the second barrier layer;
a fourth conductive layer over the second barrier layer;
a buildup layer over the second barrier layer, wherein the buildup layer comprises a dielectric material;
a fifth conductive layer through the buildup layer;
a sixth conductive layer over the buildup layer;
a first solder resist layer over the buildup layer; and
a second solder resist layer contacting a portion of the first barrier layer.

Assignees

• Intel Corp

Inventors

• Xu Cheng
• Lee Kyu-Oh
• Zhao Junnan
• Jain Rahul
• Park Ji Yong
• Vadlamani Sai
• Kim Seo Young

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/05 Primary

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title