Method and system for efficient floating-point compression

Patent metadata

Field	Value
Publication number	US-11416248-B2
Application number	US-202016833597-A
Country	US
Kind code	B2
Filing date	Mar 28, 2020
Priority date	Mar 28, 2020
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

An apparatus and method for compressing floating-point values. For example, one embodiment of a processor comprises: instruction fetch circuitry to fetch instructions from a memory, the instructions including floating-point instructions; execution circuitry to execute the floating-point instructions, each floating-point instruction having one or more floating-point operands, each floating-point operand comprising an exponent value and a significand value; floating-point compression circuitry to compress a plurality of the exponent values associated with a corresponding plurality of the floating-point operands, the floating-point compression circuitry comprising: base generation circuitry to evaluate the plurality of the exponent values to generate a first base value; and delta generation circuitry to determine a difference between the plurality of exponent values and the first base value and to generate a corresponding first plurality of delta values, wherein the floating-point compression circuitry is to store the first base value and the corresponding first plurality of delta values as a plurality of compressed exponent values.

First claim

What is claimed is:

1. A processor comprising:
instruction fetch circuitry to fetch instructions from a memory, the instructions including floating-point instructions;
execution circuitry to execute the floating-point instructions, each floating-point instruction having one or more floating-point operands, each floating-point operand comprising an exponent value and a significand value; and
floating-point compression circuitry to, in response to a first floating-point instruction, compress a plurality of the exponent values associated with a corresponding plurality of the floating-point operands, the floating-point compression circuitry comprising:
base generation circuitry to evaluate the plurality of the exponent values to generate a first base value; and
delta generation circuitry to determine a difference between each of the plurality of the exponent values and the first base value and to generate a corresponding first plurality of delta values,

wherein the floating-point compression circuitry is to store the first base value along with the corresponding first plurality of delta values as a plurality of compressed exponent values, a plurality of compression bits each for one of the plurality of compressed exponent values to indicate that the exponent value is compressed, and a corresponding plurality of significand values each for one of the plurality of compressed exponent values, wherein each compression bit for a compressed exponent value takes a bit position for a significand value corresponding to the compressed exponent value and the significand value's bit width is reduced by one.

2. The processor of claim 1 wherein the floating-point compression circuitry is to compress the plurality of the exponent values independently from any compression of the corresponding plurality of the significand values.

3. The processor of claim 1 wherein the floating-point compression circuitry is to compress the corresponding plurality of significand values using a different compression technique from that used to generate the plurality of compressed exponent values.

4. The processor of claim 1 further comprising:
floating-point decompression circuitry to, in response to a second floating-point instruction, receive a plurality of compressed exponent values of compressed floating-point values read from the memory, the floating-point decompression circuitry to add a second base value associated with the plurality of compressed exponent values to a second plurality of delta values to generate a corresponding plurality of decompressed exponent values.

5. The processor of claim 4 wherein the floating-point decompression circuitry is to load a first floating-point value in a source register indicated by the second floating-point instruction, the first floating-point value comprising a first decompressed exponent value of the plurality of decompressed exponent values and a first significand value.

6. The processor of claim 1 wherein the corresponding plurality of the floating-point operands comprise one or more of: half-precision floating-point operands, single-precision floating-point operands, double-precision floating-point operands, bfloat16 operands, fp8 operands, and fp9 operands.

7. The processor of claim 1 wherein the first base value comprises an 8-bit value and the delta values comprise 2-bit or 3-bit values.

8. A method comprising:
fetching instructions from a memory, the instructions including floating-point instructions;
executing the floating-point instructions, each floating-point instruction having one or more floating-point operands, each floating-point operand comprising an exponent value and a significand value;
in response to a first floating-point instruction, compressing a plurality of the exponent values associated with a corresponding plurality of the floating-point operands, wherein compressing comprises:
evaluating the plurality of the exponent values to generate a first base value; and
determining a difference between each of the plurality of the exponent values and the first base value to generate a corresponding first plurality of delta values, and

storing the first base value, along with the corresponding first plurality of delta values as a plurality of compressed exponent values, a plurality of compression bits each for one of the plurality of compressed exponent values to indicate that the exponent value is compressed, and a corresponding plurality of significand values each for the one of the plurality of compressed exponent values, wherein each compression bit for a compressed exponent value takes a bit position for a significand value corresponding to the compressed exponent value and the significand value bit width is reduced by one.

9. The method of claim 8 wherein the plurality of the exponent values are to be compressed independently from any compression of the corresponding plurality of the significand values.

10. The method of claim 8 wherein the corresponding plurality of significand values are to be compressed using a different compression technique from that used to generate the plurality of compressed exponent values.

11. The method of claim 8 further comprising:
in response to a second floating-point instruction, receiving a plurality of compressed exponent values from the memory; and
adding a second base value associated with the plurality of compressed exponent values to a second plurality of delta values to generate a corresponding plurality of decompressed exponent values.

12. The method of claim 11 further comprising:
loading a first floating-point value in a source register indicated by the second floating-point instruction, the first floating-point value comprising a first decompressed exponent value of the plurality of decompressed exponent values and a first significand value.

13. The method of claim 8 wherein the corresponding plurality of the floating-point operands comprise one or more of: half-precision floating-point operands, single-precision floating-point operands, double-precision floating-point operands, bfloat16 operands, fp8 operands, and fp9 operands.

14. The method of claim 8 wherein the first base value comprises an 8-bit value and the delta values comprise 2-bit or 3-bit values.

15. A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:
fetching instructions from a memory, the instructions including floating-point instructions;
executing the floating-point instructions, each floating-point instruction having one or more floating-point operands, each floating-point operand comprising an exponent value and a significand value;
in response to a first floating-point instruction, compressing a plurality of the exponent values associated with a corresponding plurality of the floating-point operands, wherein compressing comprises:
evaluating the plurality of the exponent values to generate a first base value; and
determining a difference between each of the plurality of the exponent values and the first base value to generate a corresponding first plurality of delta values, and

storing the first base value, along with the corresponding first plurality of delta values as a plurality of compressed exponent values, a plurality of compression bits each for each one of the plurality of compressed exponent values to indicate that the exponent value is compressed, and a corresponding plurality of significand values each for the one of the plurality of compressed exponent values, wherein each compression bit for a compressed exponent value tak

Assignees

• Intel Corp

Inventors

• Sim Jaewoong
• Alameldeen Alaa
• Nurvitadhi Eriko
• Marr Deborah

Classifications

• G06F7/556

  Logarithmic or exponential functions · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F7/483 Primary

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title

• G06F7/485

  Adding; Subtracting {(G06F7/4833, G06F7/4836 take precedence)} · CPC title