Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanism
US-2025384257-A1 · Dec 18, 2025 · US
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Marr Deborah patents
Marr Deborah is listed as an inventor on 37 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Marr Deborah |
| Total patents | 37 |
| First publication | Jul 5, 2018 |
| Latest publication | Dec 18, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Machine learning accelerator mechanism
US-12417380-B2 · Sep 16, 2025 · US
Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanism
US-12380326-B2 · Aug 5, 2025 · US
Machine learning accelerator mechanism
US-2024403620-A1 · Dec 5, 2024 · US
Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanism
US-2024256845-A1 · Aug 1, 2024 · US
Machine learning accelerator mechanism
US-12039435-B2 · Jul 16, 2024 · US
Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanism
US-12014265-B2 · Jun 18, 2024 · US
Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Array Matrix Multipliers
US-2023359695-A1 · Nov 9, 2023 · US
Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanism
US-2023316058-A1 · Oct 5, 2023 · US
Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanism
US-11636327-B2 · Apr 25, 2023 · US
Recent patents
Latest publications not already listed above.
Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Array Matrix Multipliers
US-2023064381-A1 · Mar 2, 2023 · US
Machine learning accelerator mechanism
US-2023053289-A1 · Feb 16, 2023 · US
Method and system for efficient floating-point compression
US-11416248-B2 · Aug 16, 2022 · US
Machine learning accelerator mechanism
US-11373088-B2 · Jun 28, 2022 · US
Memory-size- and bandwidth-efficient method for feeding systolic array matrix multipliers
US-11328037-B2 · May 10, 2022 · US
High confidence multiple branch offset predictor
US-2022129763-A1 · Apr 28, 2022 · US
Hardware accelerator template and design framework for implementing recurrent neural networks
US-2022121917-A1 · Apr 21, 2022 · US
Hardware accelerator template and design framework for implementing recurrent neural networks
US-11216722-B2 · Jan 4, 2022 · US
Apparatus and method for a high throughput parallel co-processor and interconnect with low offload latency
US-10915328-B2 · Feb 9, 2021 · US
Architecture and method for data parallel single program multiple data (SPMD) execution
US-10831505-B2 · Nov 10, 2020 · US
Apparatus and method for adaptable and efficient lane-wise tensor processing
US-10776110-B2 · Sep 15, 2020 · US
Apparatus and method for a high throughput parallel co-processor and interconnect with low offload latency
US-2020192676-A1 · Jun 18, 2020 · US
Apparatus and method for adaptable and efficient lane-wise tensor processing
US-2020104126-A1 · Apr 2, 2020 · US
Architecture and method for data parallel single program multiple data (spmd) execution
US-2020104139-A1 · Apr 2, 2020 · US
Microarchitecture enabling enhanced parallelism for sparse linear algebra operations having write-to-read dependencies
US-10387037-B2 · Aug 20, 2019 · US
Compute engine architecture to support data-parallel loops with reduction operations
US-10372507-B2 · Aug 6, 2019 · US
Machine learning accelerator mechanism
US-2019205737-A1 · Jul 4, 2019 · US
Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanism
US-2019205746-A1 · Jul 4, 2019 · US
Heterogeneous hardware accelerator architecture for processing sparse matrix data with skewed non-zero distributions
US-10180928-B2 · Jan 15, 2019 · US
Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Array Matrix Multipliers
US-2019012295-A1 · Jan 10, 2019 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 37 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F17/16 | 20 |
| G06N20/00 | 19 |
| G06N3/0442 | 16 |
| G06N3/044 | 16 |
| G06N3/063 | 16 |