SIMD instructions for data compression and decompression

Patent metadata

Field	Value
Publication number	US-9298457-B2
Application number	US-201313747352-A
Country	US
Kind code	B2
Filing date	Jan 22, 2013
Priority date	Jan 22, 2013
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

An execution unit configured for compression and decompression of numerical data utilizing single instruction, multiple data (SIMD) instructions is described. The numerical data includes integer and floating-point samples. Compression supports three encoding modes: lossless, fixed-rate, and fixed-quality. SIMD instructions for compression operations may include attenuation, derivative calculations, bit packing to form compressed packets, header generation for the packets, and packed array output operations. SIMD instructions for decompression may include packed array input operations, header recovery, decoder control, bit unpacking, integration, and amplification. Compression and decompression may be implemented in a microprocessor, digital signal processor, field-programmable gate array, application-specific integrated circuit, system-on-chip, or graphics processor, using SIMD instructions. Compression and decompression of numerical data can reduce memory, networking, and storage bottlenecks. This abstract does not limit the scope of the invention as described in the claims.

First claim

What is claimed is:

1. A data processor, comprising:
an execution unit configured to execute single instruction multiple data (SIMD) instructions, the execution unit including logic responsive to a first SIMD instruction (V_EXPMAX) that includes a multiple data identifier that identifies multiple operands to determine a maximum exponent value of the multiple operands identified by the multiple data identifier, the execution unit including logic to pack a number of bits from each of the plurality of operands based on the maximum exponent value determined in response to the first SIMD instruction to form the compressed data group, wherein the compressed data group represents the plurality of operands.

2. The data processor of claim 1 , wherein said logic responsive to the first SIMD instruction determines a first maximum exponent value of a first subset of the multiple operands, and a second maximum exponent value of a second subset of the multiple operands, said first maximum exponent value being one of the first maximum exponent value and the second maximum exponent value.

3. The data processor of claim 1 , wherein the logic to pack is responsive to a second SIMD instruction (V_PACK_REG).

4. The data processor of claim 1 , wherein the logic to pack encodes the maximum exponent value to form an exponent token for the compressed data group.

5. The data processor of claim 1 , the execution unit including a double buffering circuit, logic to store data from compressed data groups in the double buffering circuit, and logic responsive to a conditional instruction (V_WRITE_IF_FULL) to write data from the double buffering circuit to an array having a fixed width when the double buffering circuit holds said fixed width of data.

6. A data processor, comprising:
an execution unit configured to execute single instruction multiple data (SIMD) instructions, the execution unit including logic responsive to a first SIMD instruction (V_EXPMAX) that includes a multiple data identifier that identifies multiple operands to determine a maximum exponent value of the multiple operands identified by the multiple data identifier, the execution unit including logic to map the bits of the operands to a number of nibbles , a given nibble in number of nibbles including bits selected from each of the plurality of operands based on a place value of the bits in the respective operands.

7. A data processor, comprising:
an execution unit configured to execute single instruction multiple data (SIMD) instructions, the execution unit including logic responsive to a first SIMD instruction (V_DERIV) that includes a multiple data identifier that identifies multiple operands, to calculate differences between a pairs of operands in the multiple operands identified by the multiple data identifier, to produce a plurality of difference value operands, the execution unit including logic to map the bits of the difference value operands to a number of nibbles in a data store, a given nibble in the number of nibbles including bits selected from each of the multiple operands based on a place value of the bits in the respective difference value operands.

8. The data processor of claim 7 , the execution unit including logic responsive to a second SIMD instruction (V_EXPMAX) that includes a second multiple data identifier that identifies multiple operands to determine a maximum exponent value of the multiple operands, wherein said multiple operands comprise said plurality of difference value operands.

9. A data processor, comprising:
an execution unit configured to execute single instruction multiple data (SIMD) instructions, the execution unit including logic responsive to a first SIMD instruction (V_DERIV) that includes a multiple data identifier that identifies multiple operands, to calculate differences between a pairs of operands in the multiple operands identified by the multiple data identifier, to produce a plurality of difference value operands, the execution unit including logic to pack a number of bits from each of the plurality of difference value operands based on a maximum exponent value to form a compressed data group, wherein the compressed data group represents the plurality of operands.

10. The data processor of claim 9 , wherein the logic to pack is responsive to a third SIMD instruction (V_PACK_REG).

11. The data processor of claim 9 , wherein the logic to pack encodes the maximum exponent value to form an exponent token for the compressed data group.

12. The data processor of claim 9 , the logic to pack is responsive to a fourth SIMD instruction (V_PACK_HDR) to generate a header including an attenuator setting and a derivative selector, and to include the header and one or more compressed data groups in a compressed data packet.

13. The data processor of claim 9 , the execution unit including a double buffering circuit, and logic to store one or more compressed data groups in the double buffering circuit, and logic responsive to a conditional instruction (V_WRITE_IF_FULL) to write data from the double buffering circuit to an array having a fixed width when the double buffering circuit holds said fixed width of data.

14. A data processor, comprising:
an execution unit configured to execute single instruction multiple data (SIMD) instructions, the execution unit including logic responsive to a first SIMD instruction (V_DECODE_MANTS) that includes a multiple data identifier that identifies a destination for multiple data values of constant data length, which using an exponent for a group of packed mantissas, decodes and sign-extends most significant bits for integer data types to produce the multiple data values identified by the multiple data identifier, or decodes and zero-fills least significant bits for floating point data types to produce the multiple data values identified by the multiple data identifier, wherein the compressed data packet includes packed mantissas having values attenuated by an attenuation value, and the execution unit includes logic to multiply said multiple data values by a reciprocal of said attenuation value.

15. The data processor of claim 14 , the execution unit including logic to decode a compressed data packet to obtain said exponent and said group of packed mantissas.

16. The data processor of claim 14 , the execution unit including logic responsive to a second SIMD instruction (V_INTEG) that includes a second multiple data identifier that identifies multiple operands, to calculate sums of pairs of operands in the multiple operands identified by the second multiple data identifier, to produce a plurality of integrated value operands.

17. A data processor, comprising:
an execution unit configured to execute single instruction multiple data (SIMD) instructions, the execution unit including logic responsive to
a first SIMD instruction (V_DERIV) that includes a multiple data identifier that identifies multiple operands, to calculate differences between a pairs of operands in the multiple operands identified by the multiple data identifier, to produce a plurality of difference value operands;
a second SIMD instruction (V_EXPMAX) that includes a multiple data identifier that identifies multiple operands to determine a maximum exponent value of the multiple operands identified by the multiple data identifier;
a third SIMD instruction (V_PACK_REG) pack a number of bits from each of the plurality of operands based on a maximum exponent value to form the compressed data group, wherein the compressed data group represents the plurality of operands;
a fourth SIMD instruction (V_DECODE_MANTS) that inc

Assignees

• Altera Corp

Inventors

• Wegener Albert W

Classifications

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F9/345

  of multiple operands or results {(addressing multiple banks G06F12/06)} · CPC title

• H04L12/00

  Data switching networks (interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units G06F13/00) · CPC title