Semiconductor memory device having plural chips connected by hybrid bonding method

Patent metadata

Field	Value
Publication number	US-10600772-B2
Application number	US-201916446491-A
Country	US
Kind code	B2
Filing date	Jun 19, 2019
Priority date	May 22, 2018
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

Disclosed herein is an apparatus that includes a first semiconductor chip including a plurality of memory cell arrays and a plurality of first bonding electrodes electrically connected to the memory cell arrays, and a second semiconductor chip including a logic circuits and a plurality of second bonding electrodes electrically connected to the logic circuits. The first and second semiconductor chips are stacked with each other so that each of the first bonding electrodes is electrically connected to an associated one of the second bonding electrodes.

First claim

The invention claimed is:

1. An apparatus comprising:
a first semiconductor chip comprising:
a first plurality of memory cell arrays, each disposed on an associated one of intersections of first and second signal lines;
a first plurality of bonding electrodes electrically connected respectively to corresponding first signal lines; and
a first plurality of switches configured to respectively couple one of the second signal lines to a corresponding one of the first plurality of bonding electrodes; and

a second semiconductor chip comprising:
a second plurality of memory cell arrays, each disposed on an associated one of intersections of third and fourth signal lines;
a second plurality of bonding electrodes respectively coupled to the first plurality of bonding electrodes of the first semiconductor chip and electrically connected respectively to corresponding third signal lines;
a third plurality of bonding electrodes electrically connected respectively to corresponding third signal lines and coupled to a logic chip; and
a second plurality of switches configured to respectively couple one of the fourth signal lines to a corresponding one of the second and third plurality of bonding electrodes;

wherein the first and second plurality of switches are configured to turn on/off so that one memory cell array of the first semiconductor chip and the second semiconductor chip is accessed through a corresponding one of the third plurality of bonding electrodes to the logic chip.

2. The apparatus of claim 1 , wherein the second plurality of bonding electrodes and the third plurality bonding electrodes are disposed on opposite sides of the second semiconductor chip.

3. The apparatus of claim 1 , wherein the second semiconductor chip is stacked on the first semiconductor chip and is also sandwiched between the logic chip and the first semiconductor chip.

4. The apparatus of claim 1 , wherein the first and third signal lines are bit lines and the second and fourth signal lines are sub-word lines.

5. The apparatus of claim 1 , wherein the first and second plurality of switches are configured to couple a sub-word signal supplied from a sub-word driver of the logic chip to one of the fourth signal lines through one of the third plurality of bonding electrodes in the second semiconductor chip.

6. The apparatus of claim 1 , wherein the first and second plurality of switches are configured to couple a sub-word signal supplied from a sub-word driver of the logic chip to one of the second signal lines through corresponding bounding electrodes from the first, second and third plurality of bonding electrodes.

7. The apparatus of claim 6 , wherein the first and second semiconductor chips are laminated to the logic chip in a lamination direction, and wherein the corresponding bonding electrodes from the first, second and third plurality of bonding electrodes are aligned in the lamination direction.

8. The apparatus of claim 1 , wherein the first and second semiconductor chips are laminated to the logic chip in a lamination direction, and wherein corresponding bonding electrodes from the first, second and third plurality of bonding electrodes are aligned in the lamination direction and configured to couple a bit line signal from the logic circuit to a corresponding signal line in the third signal lines and to a corresponding signal line in the first signal lines.

9. An apparatus comprising:
a first semiconductor chip comprising:
a first plurality of memory cell arrays, each disposed on an associated one of intersections of first and second signal lines;
a first plurality of bonding electrodes disposed on a top side of the first semiconductor chip; and
a first plurality of switches respectively coupled between one of the second signal lines and a corresponding one of the first plurality of bonding electrodes; and

a second semiconductor chip comprising:
a second plurality of memory cell arrays, each disposed on an associated one of intersections of third and fourth signal lines;
a second plurality of bonding electrodes disposed on a bottom side of the second semiconductor chip;
a third plurality of bonding electrodes disposed on a top side of the second semiconductor chip; and
a second plurality of switches respectively coupled between one of the fourth signal lines and a corresponding one of the second plurality of bonding electrodes and a corresponding one of the third plurality of bonding electrodes;

wherein the first and second plurality of switches are configured to couple a sub-word signal from a sub-word driver of a logic chip to one of corresponding memory cell arrays in the first semiconductor chip and the second semiconductor chip.

10. The apparatus of claim 9 , wherein the second semiconductor chip is stacked on the top side of the first semiconductor chip in a vertical direction and the logic chip is laminated to the top side of the second semiconductor chip.

11. The apparatus of claim 9 , wherein the second plurality of switches are configured to couple the sub-word signal to one of the fourth signal lines through one of the third plurality of bonding electrodes in the second semiconductor chip responsive to a selection signal.

12. The apparatus of claim 9 , wherein the first and second plurality of switches are configured to couple the sub-word signal to one of the second signal lines through corresponding bounding electrodes from the first, second and third plurality of bonding electrodes responsive to a selection signal.

13. An apparatus comprising:
a logic circuit comprising a sub-word driver circuit;
a first semiconductor chip comprising:
a first plurality of memory cell arrays each including a plurality of first signal lines extending in a first direction, a plurality of second signal lines extending in a second direction different from the first direction, and a plurality of memory cells each disposed on an associated one of intersections of the plurality of first and plurality of second signal lines; and
a first plurality of switches configured to couple a sub-word signal to one of the first plurality of memory cell arrays; and

a second semiconductor chip comprising:
a second plurality of memory cell arrays each including a plurality of third signal lines extending in the first direction, a plurality of fourth signal lines extending in the second direction, and a plurality of memory cells each disposed on an associated one of intersections of the plurality of third and the plurality of fourth signal lines; and
a second plurality of switches coupled to couple a sub-word signal from a sub-word driver circuit of the logic chip to one of the fourth signal lines;

wherein the second semiconductor chip is sandwiched between the logic chip and the first semiconductor chip.

14. The apparatus of claim 13 , wherein the first and second semiconductor chips are stacked in a vertical direction.

15. The apparatus of claim 14 , wherein a bit line from the logic chip is coupled to a corresponding signal line in the third signal lines in the second semiconductor chip and also to a corresponding signal line in the first signal lines in the first semiconductor chip.

16. The apparatus of claim 15 , wherein the bit line from the logic chip is coupled to the corresponding signal line in the third signal lines in the second semiconductor chip and also to the corresponding signal line in the first signal lines in the first semiconductor chip via one or more bonding electrodes aligned in the vertical direction.

17. The apparatus of claim 14 , the sub-word signal from the logic ch

Assignees

• Micron Technology Inc

Inventors

• Sukekawa Mitsunari

Classifications

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C5/02

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title

• G11C11/408

  Address circuits · CPC title