Three-dimensional memory device including contact via structures for multi-level stepped surfaces and methods for forming the same

Patent metadata

Field	Value
Publication number	US-11410924-B2
Application number	US-202016999388-A
Country	US
Kind code	B2
Filing date	Aug 21, 2020
Priority date	Aug 21, 2020
Publication date	Aug 9, 2022
Grant date	Aug 9, 2022

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing steps, memory stack structures extending through the alternating stack, a first contact via structure which contacts a top surface of a respective upper electrically conductive layer in a first step, a first dielectric spacer which does not contact any of the electrically conductive layers other than the respective upper electrically conductive layer in the first step, a second contact via structure which contacts a top surface of a respective lower electrically conductive layer in the first step, and a second dielectric spacer which extends through the respective upper electrically conductive layer, and which contacts the respective lower electrically conductive layer.

First claim

What is claimed is:

1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers containing a terrace region comprising a plurality of steps;
memory stack structures extending through the alternating stack;
a retro-stepped dielectric material portion overlying terrace region of the alternating stack;
first laterally isolated contact structures each including a respective first contact via structure and a respective first dielectric spacer, wherein the respective first contact via structure contacts a top surface of a respective upper electrically conductive layer of the electrically conductive layers in the respective step, and the respective first dielectric spacer extends through the retro-stepped dielectric material portion and does not contact any of the electrically conductive layers other than the respective upper electrically conductive layer in the respective step; and
second laterally isolated contact structures including a respective second contact via structure and a respective second dielectric spacer, wherein the respective second contact via structure contacts a top surface of a respective lower electrically conductive layer of the electrically conductive layers in the respective step, and the respective second dielectric spacer extends through the retro-stepped dielectric material portion and through the respective upper electrically conductive layer, and contacts the respective lower electrically conductive layer.

2. The three-dimensional memory device of claim 1 , wherein the respective second dielectric spacer extends through a via cavity and contacts a sidewall of the respective upper electrically conductive layer exposed in the via cavity.

3. The three-dimensional memory device of claim 2 , wherein the respective second dielectric spacer contacts a sidewall of a respective one of the insulating layers exposed in the via cavity.

4. The three-dimensional memory device of claim 2 , wherein the first dielectric spacers and the second dielectric spacers comprise a same dielectric material and have annular top surfaces located within a horizontal plane located above a top surface of the retro-stepped dielectric material portion.

5. The three-dimensional memory device of claim 4 , wherein the first contact via structures and the second contact via structures have top surfaces located within the horizontal plane.

6. The three-dimensional memory device of claim 2 , wherein:
an annular bottom surface of the respective first dielectric spacer contacts a top surface of the respective upper electrically conductive layer; and
an annular bottom surface of the respective second dielectric spacer contacts the respective lower electrically conductive layer.

7. The three-dimensional memory device of claim 6 , wherein a cylindrical portion of an outer sidewall of the respective second dielectric spacer contacts a cylindrical surface of the respective upper electrically conductive layer exposed in the via cavity.

8. The three-dimensional memory device of claim 2 , wherein the respective second dielectric spacer contacts cylindrical sidewalls of at least two additional upper electrically conductive layers of the electrically conductive layers exposed in the via cavity.

9. The three-dimensional memory device of claim 1 , wherein:
the retro-stepped dielectric material portion comprises a contiguous set of surfaces that includes horizontal bottom surface segments and vertical surface segments;
the horizontal bottom surface segments are vertically spaced apart from each other and are laterally spaced apart from each other; and
each of the horizontal bottom surface segments other than a bottommost one of the horizontal bottom surface segments is adjoined to a respective pair of vertical surfaces segments of the vertical surface segments of the retro-stepped dielectric material portion.

10. The three-dimensional memory device of claim 9 , wherein:
each of the insulating layers contacts has a respective sidewall that contacts a respective one of the vertical sidewall segments of the retro-stepped dielectric material portion; and
each of electrically conducive layers contacts the retro-stepped dielectric material portion, or is laterally spaced from the retro-stepped dielectric material portion by a respective backside blocking dielectric layer.

11. The three-dimensional memory device of claim 9 , wherein one the vertical sidewall segments of the retro-stepped dielectric material portion contacts sidewalls of at least two insulating layers of the insulating layers.

12. The three-dimensional memory device of claim 1 , wherein:
the alternating stack has a vertical periodicity that is the same as a vertical separation distance between top surfaces of a vertically neighboring pair of insulating layers within the alternating stack;
top surfaces of the first electrically conductive layers are vertically offset from each other by multiples of K times the vertical periodicity, wherein K is an integer in a range from 2 to 2 N , and wherein N is an integer in a range from 2 to 6; and
top surfaces of the second electrically conductive layers are vertically offset from each other multiples of K times the vertical periodicity.

13. The three-dimensional memory device of claim 1 , wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel.

14. A method of forming a three-dimensional memory device, comprising:
forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers comprise, or are subsequently replaced with, electrically conductive layers;
forming a plurality of steps by patterning the alternating stack;
forming a retro-stepped dielectric material portion over the plurality of steps;
forming a first via cavity and a second via cavity that vertically extend through the retro-stepped dielectric material portion down to a top surface of an upper electrically conductive layer of the electrically conductive layers in a first step of the plurality of steps by performing a first anisotropic etch process;
vertically extending the second via cavity through the upper electrically conductive layer and one of the insulating layers down to a top surface of a lower electrically conductive layer of the electrically conductive layers in the first step by performing a second anisotropic etch process without vertically extending the first via cavity; and
forming a first laterally isolated contact structure in the first via cavity and a second laterally isolated contact structure in the second via cavity, wherein the first laterally isolated contact structure includes a first contact via structure and a first dielectric spacer, and the second contact via structure comprises a second contact via structure and a second dielectric spacer.

15. The method of claim 14 , wherein:
the retro-stepped dielectric material portion comprises a contiguous set of surfaces that includes horizontal bottom surface segments and vertical surface segments; and
the first via cavity and the second via cavity extend through a first one of the horizontal bottom surface segments.

16. The method of claim 15 , further comprising forming an additional first via cavity and an additional second via cavity through a second one of the horizontal bottom surface segments employing the first anisotropic etch process.

17. The method of claim 14 , further comprising:
forming a first sacrificial via cavity fill structure and a second sacrificial via cav

Assignees

• Sandisk Technologies Llc

Inventors

• Suwa Haruki
• Shigemura Keisuke
• Shimada Akihiro

Classifications

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H01L27/11524

  Electricity · mapped topic