Polygon integrated circuit (IC) packaging

Patent metadata

Field	Value
Publication number	US-11410894-B2
Application number	US-201916562583-A
Country	US
Kind code	B2
Filing date	Sep 6, 2019
Priority date	Sep 6, 2019
Publication date	Aug 9, 2022
Grant date	Aug 9, 2022

Abstract

An electronic system includes two integrated circuit (IC) packages that are connected by a package to package (PP) connector. The PP connector may include cabling between a first cabling connector and a second cabling connector. The first cabling connector may be seated to a first carrier connector upon a first IC device carrier of the first IC device package. The second cabling connector may be seated to a second carrier connector upon a second IC device carrier of the second IC device package. The electronic system may further include a heat sink connected to the IC packages, to the first cabling connector, and to the second cabling connector. An IC device may route I/O data through the PP connector, effectively increasing the number of I/O routes.

First claim

What is claimed is:

1. An electronic system comprising:
a first integrated circuit (IC) device package comprising: a first carrier, a first IC device connected to a top surface of the first carrier (first carrier top surface), a first cover connected to the first IC device and connected to the first carrier top surface, a first carrier connector connected to the first carrier top surface;
a second IC device package comprising: a second carrier, a second IC device connected to a top surface of the second carrier (second carrier top surface), a second cover connected to the second IC device and connected to the second carrier top surface, a second carrier connector connected to the second carrier top surface;
a package to package (PP) connector comprising: cabling connected to a first cabling connector and to a second cabling connector, the first cabling connector seated to the first carrier connector and the second cabling connector seated to the second carrier connector, wherein a major planar top surface of the first cabling connector is coplanar with a top surface of the first cover and wherein a major planar top surface of the second cabling connector is coplanar with a top surface of the second cover; and
a first heatsink connected to the top surface of the first cover and to the major planar top surface of the first cabling connector.

2. The electronic system of claim 1 , wherein the first heatsink is further connected to the top surface of the second cover and to the major planar top surface of the second cabling connector.

3. The electronic system of claim 1 , further comprising:
a second heatsink connected to the top surface of the second cover and to the major planar top surface of the second cabling connector.

4. The electronic system of claim 1 , further comprising a spring between the first heatsink and the major planar top surface of the first cabling connector.

5. The electronic system of claim 1 , wherein the first integrated IC device package further comprises:
a second carrier connector connected to the first carrier top surface.

6. The electronic system of claim 5 , wherein the first integrated IC device package further comprises:
a filler seated to the second carrier connector.

7. The electronic system of claim 6 , wherein a major planar top surface of the filler is coplanar with the top surface of the first cover.

8. The electronic system of claim 1 , wherein the major planar top surface of the first cabling connector is coplanar with the major planar top surface of the second cabling connector.

Assignees

• IBM

Inventors

• Arvin Charles L
• Indyk Richard F
• Singh Bhupender
• Casey Jon A
• Li Shidong

Classifications

• H10D62/117

  Shapes of semiconductor bodies · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/075

  of bond wires · CPC title

• H10W72/50

  Bond wires · CPC title

• H10W40/25

  characterised by their materials · CPC title