Polygon die packaging

Patent metadata

Field	Value
Publication number	US-9911716-B2
Application number	US-201514609237-A
Country	US
Kind code	B2
Filing date	Jan 29, 2015
Priority date	Jan 29, 2015
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

A lidded or lidless flip-chip package includes two or more polygon shaped dies. The polygon dies may be interconnected to a substrate or to an interposer interconnected to a substrate. The interposer may be similarly shaped with respect to the polygon die(s). For the lidless or lidded package, the package may include underfill under the polygon dies surrounding associated interconnects. For the lidded package, the package may also include thermal interface materials, seal bands, and a lid. The polygon die package reduces shear stress between the polygon die/interposer and associated underfill as compared to square or rectangular shaped die/interposer of the same area. The polygon dies further maximize the utilization of a wafer from upon which the polygon dies are fabricated. The multi polygon die package may allow for a significant reduction of the polygon die to polygon die relative to the spacing and may reduce signal interconnect time.

First claim

The invention claimed is:

1. A multi-die packaging method comprising:
interconnecting, with first level solder interconnects, a central hexagon die to an upper surface of a hexagon interposer substrate;
interconnecting, with first level solder interconnects, a plurality of outer hexagon dies to the upper surface of the hexagon interposer substrate arranged about the central hexagon die;
applying a central underfill between the central hexagon die and the hexagon interposer substrate and applying a outer underfill between each of the outer hexagon dies and the hexagon interposer substrate,
wherein a same underfill-width separates the central hexagon die from each of the plurality of outer hexagon dies such that the central underfill does not contact any outer underfills and wherein the same underfill-width separate each adjacent outer hexagon die such that outer underfills associated with each adjacent outer hexagon dies do not contact;
interconnecting, with second level solder interconnects, a lower surface of the hexagon interposer substrate to an upper surface of a planar interposer substrate;
applying a second level underfill between the hexagon interposer substrate and the planar interposer substrate surrounding the second level solder interconnects;
applying a thermal interface material (TIM) upon the central hexagon die and upon each of the plurality of outer hexagon dies;
applying a seal band upon the upper surface of the planar interposer substrate about the perimeter of the second level solder interconnects;
applying a lid to the seal band, the applied lid in contact with each respective TIM; and
interconnecting, with third level solder interconnects, a lower surface of the planar interposer substrate to an upper surface of a motherboard substrate.

2. A multi-die package comprising:
a central hexagon die upon a hexagon interposer substrate;
a plurality of outer hexagon dies upon the hexagon interposer substrate arranged about the central hexagon die;
first level solder interconnects interconnecting the central hexagon die and an upper surface of the hexagon interposer substrate and interconnecting each of the plurality of outer hexagon dies and the upper surface of the hexagon interposer substrate;
central underfill between the central hexagon die and the hexagon interposer substrate and around the first level solder interconnects interconnecting the central hexagon die and the hexagon interposer substrate;
outer underfill between each of the outer hexagon dies and the hexagon interposer substrate and around the first level solder interconnects interconnecting respective outer hexagon dies and the hexagon interposer substrate,
wherein a same underfill-width separates the central hexagon die from each of the plurality of outer hexagon dies such that the central underfill does not contact any outer underfills and wherein the same underfill-width separate each adjacent outer hexagon die such that outer underfills associated with each adjacent outer hexagon dies do not contact;
a planar interposer substrate and a motherboard substrate;
second level solder interconnects interconnecting a lower surface of the hexagon interposer substrate to an upper surface of the planar interposer substrate second level underfill between the hexagon interposer substrate and the planar interposer substrate surrounding the second level interconnects;
third level solder interconnects interconnecting a lower surface of the planar interposer substrate to an upper surface of the mother board substrate;
a thermal interface material (TIM) upon the central hexagon die and upon each of the plurality of outer hexagon dies;
a seal band upon the upper surface of the planar interposer substrate about the perimeter of the second level solder interconnects; and
a lid that contacts the seal band and contacts each respective TIM.

Assignees

• IBM

Inventors

• Davis Taryn J
• Sinha Tuhin

Classifications

• H10W72/072

  of bump connectors · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/013

  of die-attach connectors · CPC title

• H10W72/073

  of die-attach connectors · CPC title