Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11404418-B2
Application number	US-202017035296-A
Country	US
Kind code	B2
Filing date	Sep 28, 2020
Priority date	Jul 15, 2016
Publication date	Aug 2, 2022
Grant date	Aug 2, 2022

Abstract

A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first group of fins arranged in a first region of a substrate and a second group of fins arranged in a second region of the substrate;
a first conductive material layer overlying a first fin in the first region;
a second conductive material layer overlying the first fin in the first region and a second fin in the first region;
a third conductive material layer overlying a first fin in the second region;
a fourth conductive material layer overlying the first fin in the second region and a second fin in the second region;
a first metal gate fill material overlying the second conductive material layer;
a second metal get fill material overlying the fourth conductive material layer,
wherein the first metal gate fill material and the second metal gate fill material are spaced apart from each other; and
a first work function adjustment layer between the first fin and the second fin in the first region and the second conductive material layer, and between the first fin and the second fin in the second region and the fourth conductive material layer.

2. The semiconductor device of claim 1 , wherein the work function adjustment material comprises a first work function adjustment material layer and a second work function adjustment material layer, wherein the first work function adjustment material layer and the second work function adjustment material layer comprise different materials.

3. The semiconductor device of claim 1 , wherein the fourth conductive material layer is in direct contact with the work function adjustment material layer.

4. The semiconductor device of claim 1 , wherein:
the first region comprises P-type field effect transistors and the second region comprises N-type field effect transistors,
a first portion of the first region comprises an ultra-low voltage threshold transistor,
a second portion of the first region comprises a standard voltage threshold transistor,
a first portion of the second region comprises a standard voltage threshold transistor, and
a second portion of the second region comprises an ultra-low voltage threshold transistor.

5. The semiconductor device of claim 1 , wherein the second conductive layer is between the first region and the second region.

6. The semiconductor device of claim 1 , wherein the third conductive layer is between the first region and the second region.

7. The semiconductor device of claim 1 , wherein the fourth conductive layer is between the first region and the second region.

8. The semiconductor device of claim 1 , wherein the third conductive layer is between the second conductive layer and the fourth conductive layer in a region between the first region and the second region.

9. A semiconductor device, comprising:
a first group of fins arranged in a first region of a substrate and a second group of fins arranged in a second region of the substrate;
a first conductive material layer overlying a first fin and a second fin in the first region;
a second conductive material layer overlying a first fin and a second fin in the second region;
a first work function adjustment layer between the first fin and the second fin in the first region and the first conductive material layer, and between the first fin and the second fin in the second region and the second conductive material layer;
a first metal gate fill material overlying the first conductive material layer;
a second metal gate fill material overlying the second conductive material layer,
wherein the first metal gate fill material and the second metal gate fill material are spaced apart from each other; and
a third conductive material layer between the second conductive material layer and the first fin in the second region,
wherein the third conductive material layer is between the first metal gate fill material and the second metal gate metal fill material.

10. The semiconductor device of claim 9 , further comprising a second work function adjustment layer disposed over the first work function adjustment layer, wherein the first work function adjustment layer and the second work function adjustment layer comprise different materials.

11. The semiconductor device of claim 9 , wherein the second conductive material layer is between the first metal gate fill material and the second metal gate fill material.

12. The semiconductor device of claim 9 , further comprising a fourth conductive material layer between the first fin in the first region and the first conductive material layer.

13. The semiconductor device of claim 9 , wherein the first work function adjustment layer extends continuously from the first region through the second region.

14. The semiconductor device of claim 10 , wherein the second work function adjustment layer extends continuously from the first region through the second region.

15. A semiconductor device, comprising:
a first field effect transistor (FET) including a first fin and a second FET including a second fin formed on a semiconductor substrate;
a first work function adjustment layer disposed over the first and second fins;
a second work function adjustment layer disposed over the first work function adjustment layer,
wherein the first work function adjustment layer and the second work function adjustment layer are formed of different materials;
a first conductive material layer disposed over the second work function adjustment layer over the first fin;
a second conductive material layer disposed over the second work function adjustment layer covering the second fin;
a first metal gate fill material disposed over the first conductive material layer; and
a second metal gate fill material disposed over the second conductive material layer,
wherein the first metal gate fill material and the second metal gate fill material are spaced apart from each other, and
wherein the second conductive material layer is between the first gate metal fill material and the second gate metal fill material.

16. The semiconductor device of claim 15 , wherein the first conductive material layer is in direct contact with the second work function adjustment layer.

17. The semiconductor device of claim 15 , wherein the second conductive material layer is in direct contact with the second work function adjustment layer.

18. The semiconductor device of claim 15 , wherein the first gate fill material is formed of a different material than the second gate fill material.

19. The semiconductor device of claim 15 , further comprising a third conductive material layer between the first gate metal fill material and the second gate metal fill material.

20. The semiconductor device of claim 15 , wherein the first work function adjustment layer extends continuously over the first fin and the second fin.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liao Chia-Chun
• Liang Chun-Sheng
• Wang Shu-Hui
• Chang Shih-Hsun
• Chen Yi-Jen

Classifications

• H10D64/666

  the conductor further comprising additional layers · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0177

  the gate conductors having different materials or different implants · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title