Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10276574-B2
Application number	US-201615211871-A
Country	US
Kind code	B2
Filing date	Jul 15, 2016
Priority date	Jul 15, 2016
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
forming a plurality of fins in a first and a second region defined on a semiconductor substrate,
wherein the plurality of fins includes a first fin disposed in a first portion of the first region, a second fin disposed in a second portion of the first region, a third fin disposed in a first portion of the second region, and a fourth fin disposed in a second portion of the second region;
forming a dielectric layer over the first to fourth fins and forming a work function adjustment layer over the dielectric layer;
forming a first hard mask having a first thickness covering the third and fourth fins having the dielectric layer and the work function adjustment layer;
forming a first conductive material layer over the first fin in the first portion of the first region and not over the second fin in the second portion of the first region;
forming a second conductive material layer over the first and second fins;
forming a first metal gate electrode fill material over the first and second fins in the first region;
removing the first hard mask covering the third and fourth fins;
forming a third conductive material layer over the third fin in the first portion of the second region and not over the fourth fin in the second portion of the second region;
forming a fourth conductive material layer over the third and fourth fins in the second region; and
forming a second metal gate electrode fill material over third and fourth fins in the second region.

2. The method according to claim 1 , further comprising forming a second hard mask having a second thickness covering the third and fourth fins prior to forming the first hard mask.

3. The method according to claim 2 , wherein the first thickness is greater than the second thickness.

4. The method according to claim 2 , wherein the removing the first hard mask covering the third and fourth fins includes removing the second hard mask covering the third and fourth fins.

5. The method according to claim 1 , wherein the dielectric layer comprises a high-k dielectric material.

6. The method according to claim 5 , further comprising a forming a work function adjustment material over the high-k dielectric material.

7. The method according to claim 6 , wherein the work function adjustment material comprises a first work function adjustment material layer and a second work function adjustment material layer, wherein the first work function adjustment material layer and the second work function adjustment material layer comprise different materials.

8. The method according to claim 1 , wherein the forming the first hard mask includes forming the first hard mask covering the first and second fins, and a portion of the first hard mask covering the first and second fins is removed prior to forming the first conductive material layer.

9. The method according to claim 1 , wherein the forming the third conductive layer includes forming the third conductive material layer overlying the first region, and the forming the fourth conductive layer includes forming fourth conductive material layer overlying the first region.

10. A method for manufacturing a semiconductor device, comprising:
forming a plurality of fins in a first and a second region defined on a semiconductor substrate,
wherein the plurality of fins includes a first group of fins arranged in the first region and second group of fins arranged in the second region;
forming a dielectric layer over the first region and the second region;
forming a first conductive material layer having a first thickness over the first region and the second region;
removing the first conductive material layer over a portion of the first region;
forming a second conductive material layer having a second thickness over the first region and the second region;
forming a first metal gate electrode fill material over the first region and the second region;
removing the first metal gate electrode fill material over the second region;
removing the first conductive material layer over the second region and the second conductive material layer over the second region;
forming a third conductive material layer over the first region and the second region;
removing the third conductive material layer over a portion of the second region;
forming a fourth conductive material layer over the first region and the second region; and
forming a second metal gate electrode fill material over the second region.

11. The method according to claim 10 , further comprising removing the third conductive material layer overlying the first region and removing the fourth conductive material layer overlying the first region.

12. The method according to claim 10 , wherein the dielectric layer comprises a high-k dielectric material.

13. The method according to claim 12 , further comprising a forming a work function adjustment material over the high-k dielectric material.

14. The method according to claim 13 , wherein the work function adjustment material comprises a first work function adjustment material layer and a second work function adjustment material layer, wherein the first work function adjustment material layer and the second work function adjustment material layer comprise different materials.

15. The method according to claim 10 , further comprising planarizing the first and second regions after forming the second metal gate electrode fill material over the second region.

16. A semiconductor device comprising a plurality of fins in a first and a second region defined on a semiconductor substrate,
wherein the plurality of fins includes a first group of fins arranged in the first region and a second group of fins arranged in the second region;
a dielectric layer overlying the first region and the second region;
a first conductive material layer overlying a first portion of the first region;
a second conductive material layer overlying the first portion of the first region and a second portion of the first region;
a third conductive material layer overlying a first portion of the second region;
a fourth conductive material layer overlying the first portion of the second region and a second portion of the second region;
a first metal gate fill material overlying the second conductive material layer; and
a second metal gate fill material overlying the fourth conductive material layer,
wherein the first metal gate fill material and the second metal gate fill material are separated from each other by the third conductive material layer and the fourth conductive material layer and there is no conductive material layer between the first metal gate fill material and the second metal gate fill material that overlies both the first region and the second region.

17. The semiconductor device of claim 16 , wherein the dielectric layer comprises a high-k dielectric material.

18. The semiconductor device of claim 17 , further comprising a work function adjustment material overlying the high-k dielectric material.

19. The semiconductor device of claim 18 , wherein the work function adjustment material comprises a first work function adjustment material layer and a second work function adjustment material layer, wherein the first work function adjustment material layer and the second work function adjustment material layer comprise different materials.

20. The semiconductor device of claim 16 , wherein:
the first region comprises P-type field effect transistors and the second

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liao Chia-Chun
• Liang Chun-Sheng
• Wang Shu-Hui
• Chang Shih-Hsun
• Chen Yi-Jen

Classifications

• H01L29/66545

  Electricity · mapped topic

• H01L27/0924 Primary

  Electricity · mapped topic

• H01L21/823821

  Electricity · mapped topic

• H01L29/4958

  Electricity · mapped topic

• H01L29/4975

  Electricity · mapped topic