Stacked semiconductor die assemblies with high efficiency thermal paths and associated methods

Patent metadata

Field	Value
Publication number	US-2016013115-A1
Application number	US-201414330934-A
Country	US
Kind code	A1
Filing date	Jul 14, 2014
Priority date	Jul 14, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.

First claim

I/We claim:

1 . A semiconductor die assembly, comprising:
a package support substrate; a first semiconductor die having a peripheral region and a stacking region; a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die; a thermal transfer unit having a first portion attached to the peripheral region of the first die, a second portion attached to the first portion by an adhesive, and a cavity defined by the first and second portions, wherein the second die is within the cavity such that the second die is spaced apart from the first portion by a gap; and an underfill material in the cavity, wherein the underfill material has a fillet that fills at least a lower region of the gap between the first portion of the thermal transfer unit and the second die.

2 . The semiconductor die assembly of claim 1 wherein the second die attached to the stacking region of the first die comprises a bottom second die, and the semiconductor die assembly further comprises a plurality of additional second dies stacked on the bottom second die, including an uppermost second die attached to the thermal transfer unit.

3 . The semiconductor die assembly of claim 2 wherein:
the first portion of the thermal transfer unit comprises an inner casing having a sidewall attached to the peripheral portion of the first die and a top attached to the uppermost second die; and
the second portion of the thermal transfer unit comprises an outer casing encasing the inner casing, the first die, and the stack of second dies.

4 . The semiconductor die assembly of claim 2 wherein the thermal transfer unit comprises a casing having a sidewall and a top, and the sidewall is attached to the peripheral portion of the first die and the top is attached to the uppermost second die by a thermal interface material.

5 . The semiconductor die assembly of claim 4 wherein the sidewall has a foundation attached to the package support substrate and a shoulder attached to the peripheral region of the first die, and wherein the shoulder is attached to the peripheral region by a thermal interface material.

6 . The semiconductor die assembly of claim 2 wherein the thermal transfer unit comprises a casing having sidewall and a top, the sidewall having four side panels and the top being a separate member attached to the four side panels.

7 . The semiconductor assembly of claim 2 wherein the first portion of the thermal transfer unit comprises a ring surrounding the stack of second dies, and the second portion of the thermal transfer unit comprises a cover attached to the ring with a thermal interface material.

8 . The semiconductor assembly of claim 2 wherein the first and second portions of the thermal transfer unit comprise a metal.

9 . A semiconductor die assembly, comprising:
a package support substrate; a first semiconductor die having a peripheral region and a stacking site; a plurality of second semiconductor dies arranged in a stack and mounted to the stacking site of the first die; a metal casing having first portion and a second portion, the first portion being attached to peripheral region of the first die and having an inner surface, the inner surface being spaced apart from the stack of second dies and extending upward, and the second portion enclosing the stack of second dies; and an underfill material between the stack of second dies and the first portion of the casing, wherein a portion of the underfill material engages the inner surface of the first portion.

10 . The semiconductor die assembly of claim 9 wherein the first portion of the casing is attached to the peripheral region of the first die by a thermal interface material, and the second portion of the casing is attached to the first portion of the casing by a thermal interface material.

11 . The semiconductor die assembly of claim 9 wherein;
the first portion of the casing comprises a ring having a foundation and a shoulder, the foundation being attached to the package support substrate, the shoulder being attached to the peripheral region by a thermal interface material, and the ring having a height below an uppermost second die of the plurality of second dies; and
the second portion of the casing comprises a top attached to an uppermost second die of the plurality of second dies and a sidewall pendent from the top, and wherein the sidewall of the second portion is attached to the ring by a thermal interface material.

12 . The semiconductor die assembly of claim 9 wherein the first portion of the casing comprises an inner casing having a first support attached to the peripheral region of the first die and a cap attached to an uppermost second die of the plurality of second dies, and the second portion comprises an outer casing having a top over the cap of the inner casing and a sidewall attached to the package support substrate.

13 . The semiconductor die assembly of claim 12 wherein the inner casing further comprises a second support opposite the first support, and the second support is attached to the peripheral region of the first die.

14 . The semiconductor die assembly of claim 9 wherein the first portion of the casing comprises a sidewall and a top attached to the sidewall, and the sidewall is attached to the peripheral region of the first die and the package support substrate.

15 . The semiconductor die assembly of claim 14 wherein the top is attached to the sidewall by a thermal interface material and the top is attached to an uppermost second die of the plurality of second dies by a thermal interface material.

16 . The semiconductor die assembly of claim 14 wherein the sidewall has a height not less than an elevation of an uppermost second die of the plurality of second dies.

17 . A semiconductor die assembly, comprising:
a package support substrate; a first semiconductor die attached to the package support substrate, the first die having a peripheral region and a mounting region, and the first die generating a first heat; a second semiconductor die attached to the mounting region of the first die, the second die generating a second heat less than the first heat; a casing having a metal base attached to the peripheral region of the first die and a metal cover attached to the base, wherein the base has a height; and an underfill material on an area of the peripheral region of the first die between the second die and the base of the casing, wherein the underfill material extends upward along the height of the base.

18 . The semiconductor device of claim 17 wherein the base comprises a ring and the cover comprises a top attached to the ring by a thermal interface material.

19 . The semiconductor device of claim 18 wherein the cover further comprises a sidewall pendent from the top, and wherein the sidewall is attached to the ring.

20 . The semiconductor device of claim 18 wherein the base comprises a sidewall extending to an elevation of an uppermost second die and the top is a flat panel connected to the sidewall.

21 . A semiconductor die assembly comprising:
a package support substrate; a first semiconductor die having a peripheral region and a stacking site; a plurality of second semiconductor dies arranged in a stack and mounted to the stacking site of the first die; a casing having first portion and a second portion, the first portion being attached to peripheral region of the first die, and the casing having a cavity encl

Assignees

• Micron Technology Inc

Inventors

• Vadhavkar Sameer S
• Li Xiao
• Groothuis Steven K
• Li Jian
• Gandhi Jaspreet S
• Derderian James M
• Hembree David R

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/28 Primary

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W72/01

  Manufacture or treatment · CPC title