Methods and apparatus to perform erase-suspend operations in memory devices

Patent metadata

Field	Value
Publication number	US-11402996-B2
Application number	US-201916271572-A
Country	US
Kind code	B2
Filing date	Feb 8, 2019
Priority date	Mar 30, 2016
Publication date	Aug 2, 2022
Grant date	Aug 2, 2022

Abstract

A disclosed example to use an erase-suspend feature on a memory device includes a host interface to receive a first erase command to perform an erase operation; and a control circuit to: based on the erase-suspend feature being enabled at the memory device, suspend the erase operation based on determining that a length of time equal to an erase segment duration value has elapsed, the length of time elapsed being relative to a start of an erase segment, and the erase segment duration value specified in a configuration parameter for the erase-suspend feature; perform a second memory operation when the erase operation is suspended; and after the second memory operation is complete, resume the erase operation based on receiving a second erase command from the memory host controller.

First claim

What is claimed is:

1. An apparatus to use an erase-suspend feature on a memory device, the apparatus comprising:
a host interface to receive a first erase command to perform an erase operation; and
a control circuit to:
based on the erase-suspend feature being enabled at the memory device, suspend the erase operation based on determining that (a) a length of time equal to an erase segment duration value has elapsed and (b) the erase operation has reached one of a plurality of suspend points associated with a block of memory to be erased, the length of time elapsed being relative to a start of an erase segment, and the erase segment duration value specified in a configuration parameter for the erase-suspend feature;
perform a second memory operation when the erase operation is suspended; and
after the second memory operation is complete, resume the erase operation based on receiving a second erase command.

2. An apparatus of claim 1 , wherein the host interface is to receive the first erase command from a memory host controller.

3. An apparatus of claim 1 , wherein the control circuit is to resume the erase operation on a subsequent erase segment following the erase segment that finished before the suspending of the erase operation.

4. An apparatus of claim 1 , wherein the host interface is further to receive an erase-suspend enable setting and the erase segment duration value, the erase-suspend enable setting to cause the memory device to perform the erase operation as a plurality of erase segments and to suspend the erase operation between the erase segments.

5. An apparatus of claim 4 , further including a feature set register to store the erase-suspend enable setting, and a trim set register to store the erase segment duration value.

6. An apparatus of claim 4 , wherein the erase-suspend enable setting and the erase segment duration value are received by the host interface during a power-up phase of the memory device.

7. An apparatus of claim 4 , wherein the erase-suspend enable setting and the erase segment duration value are received by the host interface after the memory device has operated without the erase-suspend feature being enabled.

8. An apparatus of claim 1 , further including:
one or more processors;
a network interface in communication with the one or more processors; and
the memory device in circuit with the one or more processors, the memory device including the host interface and the control circuit.

9. At least one article of manufacture comprising machine readable instructions that, when executed, cause a memory device to at least:
start an erase operation;
based on an erase-suspend feature being enabled at the memory device, suspend the erase operation based on determining that (a) a length of time equal to an erase segment duration value has elapsed and (b) the erase operation has reached one of a plurality of suspend points associated with a block of memory to be erased, the length of time elapsed being relative to a start of an erase segment, and the erase segment duration value specified in a configuration parameter for the erase-suspend feature;
perform a second memory operation when the erase operation is suspended; and
after the second memory operation is complete, resume the erase operation based on receiving an erase command.

10. At least one article of manufacture of claim 9 , wherein the instructions are to cause the memory device to start the erase operation based on a second erase command from a memory host controller before the erase command.

11. At least one article of manufacture of claim 9 , wherein the instructions are to cause the memory device to resume the erase operation on a subsequent erase segment following the erase segment that finished before the suspending of the erase operation.

12. At least one article of manufacture of claim 9 , wherein the instructions are further to cause the memory device to receive an erase-suspend enable setting and the erase segment duration value, the erase-suspend enable setting to cause the memory device to perform the erase operation as a plurality of erase segments and to suspend the erase operation between the erase segments.

13. At least one article of manufacture of claim 12 , wherein the instructions are further to cause the memory device to program a feature set register of the memory device based on the erase-suspend enable setting, and program a trim set register of the memory device based on the erase segment duration value.

14. At least one article of manufacture of claim 12 , wherein the instructions are to cause the memory device to receive the erase-suspend enable setting and the erase segment duration value during a power-up phase of the memory device.

15. At least one article of manufacture of claim 12 , wherein the instructions are to cause the memory device to receive the erase-suspend enable setting and the erase segment duration value after the memory device has operated without the erase-suspend feature being enabled.

16. A method to use an erase-suspend feature on a memory device, the method comprising:
starting, at the memory device, an erase operation;
based on the erase-suspend feature being enabled at the memory device, suspending the erase operation based on determining that (a) a length of time equal to an erase segment duration value has elapsed and (b) the erase operation has reached one of a plurality of suspend points associated with a block of memory to be erased, the length of time elapsed being relative to a start of an erase segment, and the erase segment duration value specified in a configuration parameter for the erase-suspend feature;
performing, by the memory device, a second memory operation when the erase operation is suspended; and
after the second memory operation is complete, resuming the erase operation based on receiving an erase command.

17. A method of claim 16 , wherein the erase operation is started based on a second erase command from a memory host controller before the erase command.

18. A method of claim 16 , wherein the resuming of the erase operation is performed by resuming the erase operation on a subsequent erase segment following the erase segment that finished before the suspending of the erase operation.

19. A method of claim 16 , further including receiving an erase-suspend enable setting and the erase segment duration value at the memory device, the erase-suspend enable setting to cause the memory device to perform the erase operation as a plurality of erase segments and to suspend the erase operation between the erase segments.

20. A method of claim 19 , further including programming a feature set register of the memory device based on the erase-suspend enable setting, and programming a trim set register of the memory device based on the erase segment duration value.

21. A method of claim 19 , wherein the erase-suspend enable setting and the erase segment duration value are received at the memory device during a power-up phase of the memory device.

22. A method of claim 19 , wherein the erase-suspend enable setting and the erase segment duration value are received at the memory device after the memory device has operated without the erase-suspend feature being enabled.

Assignees

• Intel Corp

Inventors

• Madraswala Aliasgar S
• Wakchaure Yogesh B
• Jaramillo Camila
• Bemalkhedkar Trupti

Classifications

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title

• G11C16/225

  Preventing erasure, programming or reading when power supply voltages are outside the required ranges · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0652 Primary

  Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket · CPC title