Methods and apparatus to perform erase-suspend operations in memory devices

Patent metadata

Field	Value
Publication number	US-10203884-B2
Application number	US-201615085291-A
Country	US
Kind code	B2
Filing date	Mar 30, 2016
Priority date	Mar 30, 2016
Publication date	Feb 12, 2019
Grant date	Feb 12, 2019

Abstract

A disclosed example to use an erase-suspend feature with a memory device includes sending, by a memory host controller, an erase-suspend enable setting and an erase segment duration value to the memory device. The erase-suspend enable setting is to cause the memory device to perform an erase operation as a plurality of erase segments and to suspend the erase operation between the erase segments. The erase segment duration value is to specify a length of time for the erase segments. The memory host controller initiates an erase operation to be performed at the memory device. When the erase operation is suspended, the memory host controller initiates a second memory operation to be performed at the memory device. After the memory host controller determines that the second memory operation is complete, the memory host controller initiates resumption of the erase operation.

First claim

What is claimed is:

1. A method to use an erase-suspend feature with a memory device, the method comprising:
sending, by a memory host controller, an erase-suspend enable setting and a separate erase segment duration value to the memory device, when the erase-suspend enable setting is set to a first value, the first value is to enable an auto erase-suspend feature in the memory device, the auto erase-suspend feature to cause the memory device: (a) to perform a first erase segment of an erase operation, (b) to, between the first erase segment and a second erase segment of the erase operation, suspend the erase operation after an elapsed length of time of the first erase segment satisfies the erase segment duration value, and (c) to resume the erase operation by performing the second erase segment;
initiating, by the memory host controller, the erase operation to be performed at the memory device;
when the erase operation is suspended, initiating, by the memory host controller, a memory operation to be performed at the memory device; and
after the memory host controller determines that the memory operation is complete, initiating, by the memory host controller, resumption of the erase operation.

2. A method of claim 1 , wherein the initiating of the resumption of the erase operation is performed by the memory host controller sending an erase command to the memory device to resume the erase operation on the second erase segment following the first erase segment that finished before the suspending of the erase operation.

3. A method of claim 1 , wherein the initiating of the memory operation is performed by the memory host controller after determining from a status register value that the memory device has suspended the erase operation.

4. A method of claim 1 , wherein the sending of the erase-suspend enable setting to the memory device is to program a feature set register of the memory device to cause the memory device to suspend the erase operation between the first and second erase segments.

5. A method of claim 1 , wherein the sending of the erase segment duration value to the memory device is to program a trim set register of the memory device.

6. A method of claim 1 , wherein the sending of the erase-suspend enable setting and the erase segment duration value to the memory device is performed by the memory host controller during a power-up phase of the memory device.

7. A method of claim 1 , wherein the sending of the erase-suspend enable setting and the erase segment duration value to the memory device is performed by the memory host controller during operation of the memory device when the memory host controller determines to change an erase-suspend configuration of the memory device between the erase-suspend feature being disabled and the erase-suspend feature being enabled.

8. A method of claim 7 , further including determining when to change the erase-suspend configuration of the memory device based on memory commands pending in a command queue of the memory host controller.

9. An apparatus to use an erase-suspend feature with a memory device, the apparatus comprising:
a memory interface to send an erase-suspend enable setting and a separate erase segment duration value to the memory device, when the erase-suspend enable setting is set to a first value, the first value is to enable an auto erase-suspend feature in the memory device, the auto erase-suspend feature to cause the memory device: (a) to perform a first erase segment of an erase operation, (b) to, between the first erase segment and a second erase segment of the erase operation, suspend the erase operation after an elapsed length of time of the first erase segment satisfies the erase segment duration value, and (c) to resume the erase operation by performing the second erase segment; and
a memory host processor to:
initiate a memory operation to be performed at the memory device when the erase operation is suspended; and
after the memory operation is complete, initiate resumption of the erase operation.

10. An apparatus of claim 9 , wherein the memory host processor is to initiate the resumption of the erase operation by sending an erase command to the memory device to resume the erase operation on the second erase segment following the first erase segment that finished before the suspending of the erase operation.

11. An apparatus of claim 9 , wherein the memory host processor is to initiate the memory operation after a determination from a status register value that the memory device has suspended the erase operation.

12. An apparatus of claim 9 , wherein the memory interface is to send the erase-suspend enable setting to the memory device to program a feature set register of the memory device, the programming of the feature set register based on the erase-suspend enable setting is to cause the memory device to suspend the erase operation between the first and second erase segments.

13. An apparatus of claim 9 , wherein the memory interface is to send the erase segment duration value to the memory device to program a trim set register of the memory device.

14. An apparatus of claim 9 , wherein the memory interface is to send the erase-suspend enable setting and the erase segment duration value to the memory device during a power-up phase of the memory device.

15. An apparatus of claim 9 , wherein the memory interface is to send the erase-suspend enable setting and the erase segment duration value to the memory device during operation of the memory device when the memory host processor determines to change an erase-suspend configuration of the memory device between the erase-suspend feature being disabled and the erase-suspend feature being enabled.

16. An apparatus of claim 15 , wherein the host processor is to determine when to change the erase-suspend configuration of the memory device based on memory commands pending in a command queue of a memory host controller.

17. An apparatus of claim 9 , further including:
one or more processors;
a network interface in communication with the one or more processors; and
a memory host controller in circuit with the one or more processors, the memory host controller including the memory interface and the memory host processor.

18. At least one article of manufacture comprising machine readable instructions that, when executed, cause a memory host controller to at least:
send an erase-suspend enable setting and a separate erase segment duration value to a memory device, when the erase-suspend enable setting is set to a first value, the first value is to enable an auto erase-suspend feature in the memory device, the auto erase-suspend feature to cause the memory device: (a) to perform a first erase segment of an erase operation, (b) to, between the first erase segment and a second erase segment of the erase operation, suspend the erase operation after an elapsed length of time of the first erase segment satisfies the erase segment duration value, and (c) to resume the erase operation by performing the second erase segment;
initiate the erase operation to be performed at the memory device;
when the erase operation is suspended, initiate a memory operation to be performed at the memory device; and
after the memory host controller determines that the memory operation is complete, initiate resumption of the erase operation.

19. At least one article of manufacture of claim 18 , wherein the instructions are to cause the memory host controller to initiate the resumption of the erase operation by sending an erase command to the memor

Assignees

• Intel Corp

Inventors

• Madraswala Aliasgar S
• Wakchaure Yogesh B
• Jaramillo Camila
• Bemalkhedkar Trupti

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0652 Primary

  Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title