System and method for SoC idle power state control based on I/O operation characterization

US11399344B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11399344-B2
Application numberUS-201615003551-A
CountryUS
Kind codeB2
Filing dateJan 21, 2016
Priority dateJan 26, 2015
Publication dateJul 26, 2022
Grant dateJul 26, 2022

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A method and apparatus of a device that manages system performance by controlling power state based on information related to I/O operations is described. The device collects historical I/O information. The historical I/O information may include the number of I/O operations over a sample period of time and the inter-arrival time between I/O operations. The device further receives information related to a current I/O operation. The information of the current I/O operation may include direction, size, quality of service, and media type of the I/O operation. The device determines a power state based on the historical I/O information and the information relative to the current I/O operation to reduce power consumption while improving system efficiency and maintaining an acceptable level of system performance. The device further applies the determined power state. Other embodiments are also described and claimed.

First claim

Opening claim text (preview).

What is claimed is: 1. A non-transitory machine-readable medium having executable instructions to cause one or more processing units to perform a method to manage performance of a data processing system, the method comprising: collecting historical input/output (I/O) information about a plurality of I/O operations over a time period with a persistent storage system of an I/O subsystem for the data processing system; receiving I/O information of a current I/O operation of the data processing system; in response to the current I/O operation, selecting a reduced power state from one of a plurality of possible reduced power states for a processing core of an integrated circuit of the data processing system, wherein the reduced power state is applied to the processing core when the current I/O operation is being processed by the I/O subsystem of the data processing system, the selecting is based on at least the historical I/O information and the I/O information of the current I/O operation, the I/O information of the current I/O operation includes at least a direction of the I/O operation, wherein the direction of the I/O operation is one of read and write, and, in response to the direction of the I/O operation is write, the current I/O information is ignored in the determining of the reduced power state; issuing an I/O operation request for the current I/O operation to the I/O subsystem, wherein the processing core is in the reduced power state; and receiving a notification that the current I/O operation has completed, wherein the processing core comes out of the reduced power state. 2. The non-transitory machine-readable medium of claim 1 , wherein the method further comprises: applying the determined reduced power state to the processing core of an integrated circuit of the data processing system. 3. The non-transitory machine-readable medium of claim 1 , wherein, in response to the direction of the I/O operation is read, the determining of the reduced power state comprises selecting a power state of high power consumption level and low latency. 4. The non-transitory machine-readable medium of claim 1 , wherein the I/O information of the current I/O operation comprises a size of the I/O operation, wherein the size of the I/O operation comprises an amount of data involved in the I/O operation. 5. The non-transitory machine-readable medium of claim 4 , wherein the current I/O operation is a first I/O operation and the reduced power state is a first power state, the method further comprising receiving I/O information of a second I/O operation and determining a second power state based on the historical I/O information and the I/O information of the second I/O operation, wherein the size of the first I/O operation is smaller than a size of the second I/O operation, wherein the first power state is determined to have higher power consumption level and lower latency than the second power state. 6. The non-transitory machine-readable medium of claim 1 , wherein the I/O information of the current I/O operation comprises a quality of service of the current I/O operation. 7. The non-transitory machine-readable medium of claim 6 , wherein the current I/O operation is a first I/O operation and the power state is a first power state, the method further comprising receiving I/O information of a second I/O operation and determining a second power state based on the historical I/O information and the I/O information of the second I/O operation, wherein the quality of service of the first I/O operation is higher than a quality of service of the second I/O operation, wherein the first power state is determined to have higher power consumption level and lower latency than the second power state. 8. A computer implemented method to manage performance of a device, the method comprising: collecting historical input/output (I/O) information about a plurality of I/O operations over a time period with a persistent storage system of an I/O subsystem for the device; receiving I/O information of a current I/O operation of the device; in response to the current I/O operation, selecting a reduced power state from one of a plurality of possible reduced power states for a processing core of an integrated circuit of the device for the processor, wherein the reduced power state is applied to the processing core when the current I/O operation is being processed by the I/O subsystem of the device and the selecting is based on at least the historical I/O information and the I/O information of the current I/O operation, the I/O information of the current I/O operation includes at least a direction of the I/O operation, wherein the direction of the I/O operation is one of read and write, and, in response to the direction of the I/O operation is write, the current I/O information is ignored in the determining of the reduced power state; issuing an I/O operation request for the current I/O operation to the I/O subsystem, wherein the processing core is in the reduced power state; and receiving a notification that the current I/O operation has completed, wherein the processing core comes out of the reduced power state. 9. The method of claim 8 further comprising entering into the determined reduced power state for the processing core. 10. The method of claim 8 , wherein the I/O information of the current I/O operation comprises a size of the current I/O operation, wherein the size of the current I/O operation comprises an amount of data involved in the current I/O operation. 11. The method of claim 8 , wherein the I/O information of the current I/O operation comprises a quality of service of the current I/O operation. 12. The method of claim 8 , wherein the I/O information of the current I/O operation comprises a media type of the current I/O operation. 13. The method of claim 12 , wherein the determining of the reduced power state comprises selecting a power state of higher power consumption level and lower latency in response to the media type of the current I/O operation is solid state drive, and selecting a power state of lower power consumption level and higher latency in response to the media type of the current I/O operation is hard drive. 14. A device for performance management, the device comprising: a processing core of an integrated circuit; a memory coupled to the processor though a bus; and a process executed from the memory by the processor causes the processing core to collect historical input/output (I/O) information about a plurality of I/O operations over a time period with a persistent storage system of an I/O subsystem of the device, receive current I/O information of an I/O operation, in response to the current I/O operation, select a reduced power state from one of a plurality of possible reduced power states for the processing core, wherein the reduced power state is applied to the processing core when the current I/O operation is being processed by an I/O subsystem and the selection is based on at least the historical I/O information and the current I/O information, the I/O information of the current I/O operation includes at least a direction of the I/O operation, wherein the direction of the I/O operation is one of read and write, and, in response to the direction of the I/O operation is write, the current I/O information is ignored in the determining of the reduced power state, issue the I/O operation request for the current I/O operation to the I/O subsystem, wherein the processing core is in the reduced power state, receive a notification that the current I/O operation has completed, wherein the processing core comes out of the reduced power state.

Assignees

Inventors

Classifications

  • Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

  • G06F1/3221Primary

    of disk drive devices · CPC title

  • detecting a user operation or a tactile contact or a motion of the device · CPC title

  • controlling an operation mode according to history or models of usage information, e.g. activity schedule or time of day · CPC title

  • in wireless communication networks · CPC title

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What does patent US11399344B2 cover?
A method and apparatus of a device that manages system performance by controlling power state based on information related to I/O operations is described. The device collects historical I/O information. The historical I/O information may include the number of I/O operations over a sample period of time and the inter-arrival time between I/O operations. The device further receives information re…
Who is the assignee on this patent?
Apple Inc
What technology area does this patent fall under?
Primary CPC classification G06F1/3221. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 26 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).