System and method for initiating a reduced power mode for one or more functional blocks of a processor based on various types of mode request

Patent metadata

Field	Value
Publication number	US-9690353-B2
Application number	US-201313799524-A
Country	US
Kind code	B2
Filing date	Mar 13, 2013
Priority date	Mar 13, 2013
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

In an embodiment, a processor includes at least one functional block and a central power controller. The at least one functional block may include at least one block component and block power logic. The block power logic may be to: receive a first request to initiate a first reduced power mode in the at least one functional block, and in response to the first request, send a notification signal to a central power controller. The central power controller may be to, in response to the notification signal: store a first state of the at least one functional block, and initiate the first reduced power mode in the at least one functional block. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a functional block; and
a central power controller,
wherein the functional block of the processor includes:
at least one block component; and
block power logic to:
receive a first request from a device driver of the functional block to initiate a first reduced power mode only in the functional block, and
in response to a receipt of the first request, send, to the central power controller of the processor, a notification signal indicating the receipt of the first request from the device driver;

wherein the central power controller of the processor can receive the notification signal from the block power logic of the functional block included in the processor, wherein the central power controller of the processor can also separately receive from an operating system kernel a second request to initiate a second reduced power mode only in the functional block included in the processor, wherein the central power controller of the processor is to:
in response to the notification signal from the block power logic, store a state of the functional block included in the processor, and
in response to the second request from the operating system kernel, store the state of the functional block included in the processor.

2. The processor of claim 1 , wherein the central power controller is further to:
in response to the second request, send a command to the block power logic to initiate the second reduced power mode in the functional block.

3. The processor of claim 1 , wherein the central power controller is further to, in response to the second request, perform at least one power control action to initiate the second reduced power mode in the functional block.

4. The processor of claim 1 , wherein the central power controller is to receive the second request using at least one register bit included in the central power controller.

5. The processor of claim 1 , wherein the central power controller is further to receive the notification signal from the block power logic using the at least one register bit included in the central power controller.

6. The processor of claim 1 , wherein the block power logic is to, in response to the first request from the device driver, initiate the first reduced power mode in the functional block.

7. The processor of claim 1 , wherein the block power logic is further to initiate a third reduced power mode in the functional block without receiving any external mode request, and send the notification signal to the central power controller.

8. The processor of claim 1 , wherein the block power logic is to receive the first request from the device driver of the functional block using one or more register bits included in the block power logic.

9. The processor of claim 1 , wherein the device driver of the functional block is associated with the at least one functional block.

10. The processor of claim 1 , wherein the central power controller is to store the state of the functional block in a memory of the central power controller.

11. The processor of claim 10 , wherein the processor comprises a plurality of functional blocks, and wherein the memory comprises capacity to store state information for all of the plurality of functional blocks.

12. The processor of claim 1 , wherein the central power controller is to perform one or more power control actions to initiate the first reduced power mode, wherein the one or more power control actions comprise power gating, voltage reduction, and clock rate reduction.

13. A system comprising:
a processor including a plurality of functional blocks and a central power controller; and
a platform memory coupled to the processor,
wherein a first functional block of the processor includes:
one or more hardware block components; and
block power logic to:
receive, from a device driver of the first functional block, a first request to initiate a first reduced power mode only in the first functional block, and
in response to a receipt of the first request, send, to central power controller of the processor, a notification signal indicating the receipt of the first request from the device driver;

wherein the central power controller of the processor can receive the notification signal from the block power logic of the first functional block included in the processor,
wherein the central power controller of the processor can also separately receive from an operating system kernel a second request to initiate a second reduced power mode only in the first functional block included in the processor,
wherein the central power controller of the processor is to:
in response to receiving the notification signal from the block power logic of the first functional block, store a first state of the first functional block, and
in response to the second request from the operating system kernel, store the state of the first functional block.

14. The system of claim 13 , wherein the central power controller is further to:
in response to the second request from the operating system kernel:
perform at least one power control action to initiate the second reduced power mode in the first functional block.

15. The system of claim 13 , wherein the central power controller is to receive the second request from the operating system kernel using at least one register bit included in the central power controller.

16. The system of claim 13 , wherein the block power logic is to receive the first request from the device driver using one or more register bits included in the block power logic.

17. The system of claim 13 , wherein the block power logic of the first functional block is to perform at least one power control action to initiate the first reduced power mode in the first functional block.

18. A method, comprising:
receiving from a device driver, by block power logic included in a first functional block of a processor, a first request to initiate a first reduced power mode only in the first functional block of the processor;
in response to a receipt of the first request, sending to a central power controller of the processor, by the block power logic of the first functional block, a notification signal indicating the receipt of the first request from the device driver, wherein the central power controller of the processor can receive the notification signal from the block power logic of the first functional block, wherein the central power controller of the processor can also separately receive from an operating system kernel a second request to initiate a second reduced power mode only in the first functional block of the processor;
storing, by the central power controller of the processor, a state of the first functional block in a first storage, wherein the storing can be in response to the notification signal from the block power logic of the first functional block or to the second request from the operating system kernel.

19. The method of claim 18 , wherein receiving the first request from the device driver by the block power logic comprises using one or more register bits included in the block power logic.

20. The method of claim 18 , further comprising:
in response to the second request received from the operating system kernel, sending, by the central power controller of the processor, a command to the block power logic of the first functional block to initiate the second reduced power mode in the first functional block of the processor.

21. The method of claim 18 , further com

Assignees

• Intel Corp

Inventors

• Moran Douglas
• Zahir Achmed Rumi
• Knolla William
• Singh Hartej
• Bibikar Vasudev Vasu
• Jahagirdar Sanjeev
• Klinglesmith Michael
• Vaz Irwin
• George Varghese

Classifications

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• Y02B60/32

  Cross-Sectional Technologies · mapped topic

• Y02B60/1282

  Cross-Sectional Technologies · mapped topic

• G06F1/3234 Primary

  Power saving characterised by the action undertaken · CPC title

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title