Power management for a computer system

Patent metadata

Field	Value
Publication number	US-9329664-B2
Application number	US-201313966414-A
Country	US
Kind code	B2
Filing date	Aug 14, 2013
Priority date	Mar 15, 2013
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

Embodiments include a method for managing power in a computer system including a main processor and an active memory device including powered units, the active memory device in communication with the main processor by a memory link, the powered units including a processing element. The method includes the main processor executing a program on a program thread, encountering a first section of code to be executed by the active memory device, changing, by a first command, a power state of a powered unit on the active memory device based on the main processor encountering the first section of code, the first command including a store command. The method also includes the processing element executing the first section of code at a second time, changing a power state of the main processor from a power use state to a power saving state based on the processing element executing the first section.

First claim

What is claimed is:

1. A method for managing power in a computer system including a main processor and an active memory device including powered units, the active memory device in communication with the main processor by a memory link, the powered unit comprising a processing element, the method comprising:
executing, at the main processor, a program on a program thread;
encountering, at the main processor, a first section of code to be executed by the active memory device;
changing, by a first command, a power state of a powered unit on the active memory device based on the main processor encountering the first section of code, the first command comprising a store command;
executing, by the processing element, the first section of code;
changing a power state of the main processor from a power use state to a power saving state based on the processing element executing the first section of code;
changing the power state of the memory link to a power saving mode based on the processing element starting execution of the first section of code;
changing, by a second command, the power state of the main processor from the power saving state to the power use state based on the processing element completing execution of the first section of code; and
executing, by the main processor, a second section of code based on changing the power state of the main processor from the power saving state to the power use state.

2. The method of claim 1 , wherein changing the power state of the powered unit comprises changing the power state by a power management program or a controller issuing the first command across the memory link to the powered unit.

3. The method of claim 2 , wherein an address in the store command specifies an address that corresponds to the powered unit, wherein the powered unit is one of the processing element, a memory, a clock, a link controller and a interconnect, and wherein the address is not in a memory address range of the memory.

4. The method of claim 2 , wherein a payload in the store command specifies a change to the power state for the powered unit.

5. The method of claim 2 , wherein the change in the power state of the main processor and the powered units is based on states of the main processor and powered units, the state comprising one or more of: application performance, progress of individual threads and tasks of the application, power use, temperature, resource utilization and type of instructions executed.

6. The method of claim 5 , wherein the states of the main processor and powered units are obtained from at least one of: performance counters, progress counters, power proxies, thermal sensors and power supply measurements, or predicted through a compiler or application profiler, wherein a predicted state is embedded in application code as hints to the power management program or controller.

7. The method of claim 1 , wherein the powered unit comprises the processing element, the method further comprising changing the power state of the processing element to a power use state based on the processing element starting execution of the first section of code and changing the power state of the processing element to a power saving state based on the processing element completing execution of the first section of code.

8. The method of claim 1 , further comprising changing the power state of the memory link to a power use state based on the processing element completing execution of the first section of code.

9. The method of claim 1 , further comprising communicating information in a payload relating to performance and power use of the powered units on the active memory device responsive to a load command issued by a power management program or controller.

10. The method of claim 1 , wherein changing, by the first command across the memory link, the power state of the powered unit on the active memory device further comprises changing the power state of the powered unit based on an interrupt received by a power management program or controller.

Assignees

• IBM

Inventors

• Bose Pradip
• Fleischer Bruce M
• Fox Thomas W
• Jacobson Hans M
• Nair Ravi

Classifications

• Y02B60/144

  Cross-Sectional Technologies · mapped topic

• Y02B60/32

  Cross-Sectional Technologies · mapped topic

• G06F9/44

  Arrangements for executing specific programs · CPC title

• G06F9/4893

  taking into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title