Flash analog to digital converter

Patent metadata

Field	Value
Publication number	US-11394392-B2
Application number	US-202117333049-A
Country	US
Kind code	B2
Filing date	May 28, 2021
Priority date	Aug 17, 2020
Publication date	Jul 19, 2022
Grant date	Jul 19, 2022

Abstract

A flash analog to digital converter includes a voltage generator circuit, an encoder circuit, and first and second double differential amplifier circuits. The voltage generator circuit generates reference voltages according to first and second voltages. The encoder circuit generates a digital signal corresponding to an input signal according to first signals. The first double differential amplifier circuit compares the input signal with a first reference voltage in the reference voltages, to generate a corresponding one of the first signals. The second double differential amplifier circuit compares the input signal with a second reference voltage in the reference voltages, to generate a corresponding one of the first signals. A difference between the first voltage and the first reference voltage is less than that between the first voltage and the second reference voltage, and the first and the second double differential amplifier circuits have different circuit architectures.

First claim

What is claimed is:

1. A flash analog to digital converter, comprising:
a voltage generator circuit configured to generate a first set of reference voltages according to a first voltage and a second voltage;
an encoder circuit configured to generate a digital signal corresponding to an input signal according to a plurality of first signals;
a first double differential amplifier circuit configured to compare the input signal with a first reference voltage in the first set of reference voltages, in order to generate a corresponding one of the plurality of first signals; and
a second double differential amplifier circuit configured to compare the input signal with a second reference voltage in the first set of reference voltages, in order to generate a corresponding one of the plurality of first signals,
wherein a difference between the first voltage and the first reference voltage is less than a difference between the first voltage and the second reference voltage, and the first double differential amplifier circuit and the second double differential amplifier circuit have different circuit architectures.

2. The flash analog to digital converter of claim 1 , wherein the first reference voltage is a voltage closet to the first voltage in the first set of reference voltages.

3. The flash analog to digital converter of claim 1 , wherein the first double differential amplifier circuit comprises a first current path between a first power rail and a second power rail, the second double differential amplifier circuit comprises a second current path between the first power rail and the second power rail, and a number of stacked transistors in the first current path is less than a number of stacked transistors in the second current path.

4. The flash analog to digital converter of claim 1 , further comprising:
a third double differential amplifier circuit configured to compare the input signal with a third reference voltage in the first set of reference voltages, in order to generate a corresponding one of the plurality of first signals,
wherein a difference between the second voltage and the third reference voltage is less than a difference between the second voltage and the second reference voltage, and the third double differential amplifier circuit and the second double differential amplifier circuit have different circuit architectures.

5. The flash analog to digital converter of claim 4 , wherein the first double differential amplifier circuit and the third double differential amplifier circuit have the same circuit architecture.

6. The flash analog to digital converter of claim 4 , wherein the third reference voltage is a voltage closet to the second voltage in the first set of reference voltages.

7. The flash analog to digital converter of claim 4 , wherein the third double differential amplifier circuit comprises a first current path between a first power rail and a second power rail, the second double differential amplifier circuit comprises a second current path between the first power rail and the second power rail, and a number of stacked transistors in the first current path is less than a number of stacked transistors in the second current path.

8. The flash analog to digital converter of claim 1 , wherein the first double differential amplifier circuit is a portion of a first comparator circuit, and the second double differential amplifier circuit is a portion of a second comparator circuit.

9. The flash analog to digital converter of claim 1 , wherein the first double differential amplifier circuit is a folded cascode amplifier circuit.

10. The flash analog to digital converter of claim 1 , further comprising:
an interpolation network configured to perform an interpolation according to the plurality of first signals, in order to generate a plurality of second signals,
wherein the encoder circuit is further configured to encode the plurality of second signals to generate the digital signal.

11. The flash analog to digital converter of claim 10 , wherein the interpolation network comprises:
a plurality of amplifier circuits, wherein each of the plurality of amplifier circuits is configured to generate a corresponding one of the plurality of second signals according to one or two of the plurality of first signals.

12. The flash analog to digital converter of claim 11 , further comprising:
a plurality of latch circuits configured to generate a plurality of third signals according to the plurality of second signals,
wherein the encoder circuit is configured to encode the plurality of third signals to generate the digital signal.

13. The flash analog to digital converter of claim 1 , wherein the reference voltage generator circuit comprises:
a plurality of resistors configured to operate as a voltage divider circuit, in order to generate the first set of reference voltages according to the first voltage and the second voltage.

14. The flash analog to digital converter of claim 1 , further comprising:
a plurality of latch circuits configured to generate a plurality of second signals according to the plurality of first signals,
wherein the encoder circuit is configured to encode the plurality of second signals to generate the digital signal.

Assignees

• Realtek Semiconductor Corp

Inventors

• Wu Chien-Ming
• Huang Shih-Hsiung

Classifications

• H03M1/206

  using a logic interpolation circuit · CPC title

• H03M1/205 Primary

  using resistor strings for redistribution of the original reference signals or signals derived therefrom · CPC title

• H03F3/45192

  Folded cascode stages · CPC title

• H03F2203/45702

  the LC comprising two resistors · CPC title

• H03M1/365

  the voltage divider being a single resistor string · CPC title