Three-dimensional memory device containing oxidation-resistant contact structures and methods of making the same

Patent metadata

Field	Value
Publication number	US-11393757-B2
Application number	US-202016952526-A
Country	US
Kind code	B2
Filing date	Nov 19, 2020
Priority date	Nov 19, 2020
Publication date	Jul 19, 2022
Grant date	Jul 19, 2022

Abstract

A semiconductor structure includes semiconductor devices located on a top surface of a substrate semiconductor layer, lower-level metal interconnect structures, source-level material layers, and a three-dimensional memory array including an alternating stack of insulating layers and electrically conductive layers and memory stack structures vertically extending through the alternating stack and comprising a respective vertical semiconductor channel and a respective memory film. A vertically alternating sequence of insulating plates and dielectric material plates is laterally surrounded by the alternating stack. A through-memory-level interconnection via structure vertically extends through each plate within the vertically alternating sequence and contacts a center portion of a top surface of one of the lower-level metal interconnect structures. At least one silicon nitride liner prevents or reduces oxidation of the lower-level metal interconnect structures underneath the through-memory-level interconnection via structure.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
semiconductor devices located on a top surface of a substrate semiconductor layer;
lower-level metal interconnect structures embedded in lower-level dielectric material layers and electrically connected to the semiconductor devices and overlying the substrate semiconductor layer;
source-level material layers overlying the lower-level dielectric material layers and comprising an opening therethrough;
an alternating stack of insulating layers and electrically conductive layers overlying the source-level material layer;
memory stack structures vertically extending through the alternating stack and comprising a respective vertical semiconductor channel and a respective memory film;
a vertically alternating sequence of insulating plates and dielectric material plates laterally surrounded by the alternating stack;
a first through-memory-level interconnection via structure vertically extending through each plate within the vertically alternating sequence and contacting a center portion of a top surface of one of the lower-level metal interconnect structures;
at least one silicon nitride liner contacting a peripheral portion of the top surface of the one of the lower-level metal interconnect structures and contacting a cylindrical bottom end portion of a sidewall of the first through-memory-level interconnection via structure, wherein the at least one silicon nitride liner comprises a first conformal silicon nitride liner contacting each plate within the vertically alternating sequence; and
a first conformal silicon oxide liner contacting an inner cylindrical sidewall of the conformal silicon nitride liner and laterally surrounding the first through-memory-level interconnection via structure.

2. The semiconductor structure of claim 1 , wherein an interfacial portion of the first conformal silicon oxide liner comprises a nitrogen-doped surface region having a variable atomic concentration of nitrogen atoms that decreases with a distances from the first conformal silicon nitride liner.

3. The semiconductor structure of claim 1 , further comprising a first insulating spacer that contacts and laterally surrounds the first through-memory-level interconnection via structure and laterally surrounded by the first conformal silicon oxide liner.

4. A semiconductor structure, comprising:
semiconductor devices located on a top surface of a substrate semiconductor layer;
lower-level metal interconnect structures embedded in lower-level dielectric material layers and electrically connected to the semiconductor devices and overlying the substrate semiconductor layer;
source-level material layers overlying the lower-level dielectric material layers and comprising an opening therethrough;
an alternating stack of insulating layers and electrically conductive layers overlying the source-level material layer;
memory stack structures vertically extending through the alternating stack and comprising a respective vertical semiconductor channel and a respective memory film;
a vertically alternating sequence of insulating plates and dielectric material plates laterally surrounded by the alternating stack;
a first through-memory-level interconnection via structure vertically extending through each plate within the vertically alternating sequence and contacting a center portion of a top surface of one of the lower-level metal interconnect structures; and
at least one silicon nitride liner contacting a peripheral portion of the top surface of the one of the lower-level metal interconnect structures and contacting a cylindrical bottom end portion of a sidewall of the first through-memory-level interconnection via structure,
wherein the at least one silicon nitride liner comprises a planar silicon nitride liner located entirely below a horizontal plane including a bottom surface of the source-level material layers,
wherein the planar silicon nitride liner contacts an entirety of a periphery of the top surface of the one of the lower-level metal interconnect structures, and
wherein the planar silicon nitride liner laterally extends at least 300 nm from an edge of the first through-memory-level via structure.

5. The semiconductor structure of claim 4 , wherein the at least one silicon nitride liner has a thickness in a range from 4 nm to 40 nm.

6. A semiconductor structure, comprising:
semiconductor devices located on a top surface of a substrate semiconductor layer;
lower-level metal interconnect structures embedded in lower-level dielectric material layers and electrically connected to the semiconductor devices and overlying the substrate semiconductor layer;
source-level material layers overlying the lower-level dielectric material layers and comprising an opening therethrough;
an alternating stack of insulating layers and electrically conductive layers overlying the source-level material layer;
memory stack structures vertically extending through the alternating stack and comprising a respective vertical semiconductor channel and a respective memory film;
a vertically alternating sequence of insulating plates and dielectric material plates laterally surrounded by the alternating stack;
a first through-memory-level interconnection via structure vertically extending through each plate within the vertically alternating sequence and contacting a center portion of a top surface of one of the lower-level metal interconnect structures;
at least one silicon nitride liner contacting a peripheral portion of the top surface of the one of the lower-level metal interconnect structures and contacting a cylindrical bottom end portion of a sidewall of the first through-memory-level interconnection via structure, wherein the at least one silicon nitride liner comprises a planar silicon nitride liner located entirely below a horizontal plane including a bottom surface of the source-level material layers;
a conformal silicon nitride liner contacting each plate within the vertically alternating sequence; and
a first conformal silicon oxide liner contacting each plate within the vertically alternating sequence and laterally surrounding the conformal silicon nitride liner and the first through-memory-level interconnection via structure.

7. A method of forming a semiconductor structure, comprising:
forming semiconductor devices on a top surface of a substrate semiconductor layer;
forming lower-level metal interconnect structures embedded in lower-level dielectric material layers and electrically connected to the semiconductor devices over the substrate semiconductor layer;
forming a three-dimensional array of memory elements over the lower-level dielectric material layers, wherein the three-dimensional array of memory elements comprises an alternating stack of insulating layers and electrically conductive layers overlying a source-level material layer, memory stack structures vertically extending through the alternating stack and comprising a respective vertical semiconductor channel and a respective memory film, and a vertically alternating sequence of insulating plates and dielectric material plates laterally surrounded by the alternating stack;
forming a first through-memory-level via cavity through each plate within the vertically alternating sequence; and
forming a first through-memory-level interconnection via structure in the first through-memory-level via cavity,
wherein:
the first through-memory-level interconnection via structure contacts a center portion of a top surface of one of the lower-level metal interconnect structures;
at least one silicon nitride liner contacts a peripheral portion of the top surface of the one of the lower-level metal interconnect structures and contacts a cylindrical bottom end portion of a sidewa

Assignees

• Sandisk Technologies Llc

Inventors

• Takii Eisuke
• Hashimoto Hiraku
• Koyama Shin

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title