Through-memory-level via structures for a three-dimensional memory device

Patent metadata

Field	Value
Publication number	US-9818693-B2
Application number	US-201615269017-A
Country	US
Kind code	B2
Filing date	Sep 19, 2016
Priority date	Dec 22, 2015
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

First claim

What is claimed is:

1. A three dimensional NAND memory device, comprising:
word line driver devices located on or over a substrate;
at least one lower level dielectric layer overlying the word line driver devices;
lower level metal interconnect structures embedded in the at least one lower level dielectric layer;
a planar semiconductor material layer overlying the at least one lower level dielectric layer;
an alternating stack of word lines and insulating layers located over the word line driver devices and the planar semiconductor material layer;
a plurality of memory stack structures extending through the alternating stack, each memory stack structure comprising a memory film and a vertical semiconductor channel; and
through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices;

wherein:
each of the through-memory-level via structures vertically extend at least from a first horizontal plane including a topmost surface of the alternating stack to a second horizontal plane including top surfaces of a subset of the lower level metal interconnect structures that is located below the planar semiconductor material layer through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

2. The device of claim 1 , wherein the through-memory-level via structures extend through a dielectric fill material portion located in the through-memory-level via region.

3. The device of claim 2 , wherein the word line driver devices are located under the dielectric fill material portion located in the through-memory-level via region.

4. The device of claim 1 , wherein the alternating stack of word lines and insulating layers and the plurality of memory stack structures are located over the word line driver devices.

5. The device of claim 1 , wherein the through-memory-level via structures extend through at least one second alternating stack located in the through-memory-level via region.

6. The device of claim 5 , wherein:
the at least one second alternating stack includes alternating layers of dielectric spacer layers and second portions of the insulating layers, and each of the dielectric spacer layers is located at a same level as a respective word line; and
the at least one second alternating stack is at least partially surrounded by an insulating moat trench structure.

7. The device of claim 1 , wherein:
the through-memory-level via structures extend through the alternating stack of word lines and insulating layers which extends into the through-memory-level via region; and
each of the at least one through-memory-level via structures is laterally electrically isolated from the word lines by a respective insulating liner.

8. The device of claim 1 , further comprising:
word line contact via structures extending through a dielectric material portion that overlies the staircase region of the first memory block and contacting the word lines in the first memory block; and
upper level metal interconnect structures electrically shorting respective pairs of a word line contact via structure and a through-memory-level via structure, wherein the upper level metal interconnect structures overly the alternating stack, and straddle the first memory block and the dielectric fill material portion.

9. The device of claim 8 , wherein the through-memory-level via region is located in a second memory block at a first end of memory array region, and wherein no word line contact via structures are located in the through-memory-level via region in the second memory block at the first end of memory array region.

10. The device of claim 9 , further comprising:
a second staircase region in the second memory block at a second end of memory array region; and
second word line contact via structures extending through a dielectric material portion that overlies the staircase region of the second memory block and contacting the word lines in the second memory block.

11. The device of claim 1 , wherein the staircase region of the first memory block and the staircase region of another memory block ascend in a same diagonal direction.

12. The device of claim 1 , wherein the continuous vertical sidewall of the dielectric material vertically extends at least from the first horizontal plane to the second horizontal plane.

13. The device of claim 1 , wherein the dielectric material is embodied as a dielectric fill material portion that vertically extends at least from the first horizontal plane to the second horizontal plane and laterally bounded by the vertical sidewalls of the dielectric material, and each layer of the alternating stack does not extend into the through-memory-level via region.

14. The device of claim 13 , wherein the dielectric fill material portion includes sidewalls that vertically extends at least from the first horizontal plane to the second horizontal plane.

15. The device of claim 13 , wherein all surfaces of the through-memory-level via structures between the first horizontal plane and the second horizontal plane directly contacts the dielectric fill material portion.

16. The device of claim 1 , wherein the dielectric material is embodied as a single insulating liner layer that laterally surrounds each of the through-memory-level via structures, and each layer of the alternating stack does not extend into the through-memory-level via region.

17. The device of claim 16 , wherein the single insulating liner layer is located within a moat trench that laterally surrounds first material layers and second material layers, wherein the first material layers include a same material as the insulating layers, and the second material layers include a dielectric material.

18. The device of claim 1 , wherein the dielectric material is embodies as a plurality of insulating liners, and each of the plurality of insulating liners laterally surrounds a respective one of the through-memory-level via structures.

19. The device of claim 1 , further comprising:
word line contact via structures contacting a top surface of a respective one of the electrically conductive layers; and
upper level metal interconnect structures overlying the staircase region of the first memory block and contacting top surfaces of a subset of the through-memory-level via structures.

20. The device of claim 1 , further comprising a dielectric material located in the through-memory-level via region, wherein a continuous vertical sidewall of the dielectric material contacts sidewalls of each layer within the alternating stack.

Assignees

• Sandisk Technologies Llc

Inventors

• Toyama Fumiaki
• Ogawa Hiroyuki
• Furihata Yoko
• Kai James
• Mizutani Yuki
• Yu Jixin
• Liu Jin
• Alsmeier Johann

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title