SAR analog-to-digital converter calibration

Patent metadata

Field	Value
Publication number	US-11387838-B1
Application number	US-202117207343-A
Country	US
Kind code	B1
Filing date	Mar 19, 2021
Priority date	Mar 19, 2021
Publication date	Jul 12, 2022
Grant date	Jul 12, 2022

Abstract

Embodiments of the present disclosure include techniques for calibrating analog-to-digital converters (ADCs), such as successive approximation register SAR ADCs. In one embodiment, a pattern is applied to the input of an ADC to produce digital output codes. Counts of the digital output codes are used detect errors and adjust a clock delay of a comparator in the ADC. In other embodiments, an ADC calibration circuit is coupled to a calibration algorithm executing on a remote server to calibrate one or more ADCs.

First claim

What is claimed is:

1. A circuit comprising:
a successive approximation register analog-to-digital converter configured to receive an analog input signal and to generate a plurality of digital output codes corresponding to a plurality of analog input signal values of the analog input signal, the analog-to-digital converter including at least one comparator used to generate the digital output codes, wherein the at least one comparator is coupled to a comparator clock signal; and
a calibration circuit coupled to the analog-to-digital converter, the calibration circuit providing an input signal pattern to the analog-to-digital converter to generate a plurality of counts of the digital output codes across a range of analog input signal values, wherein each of the plurality of counts indicates a number of times a particular digital output code corresponding to a particular analog input signal value was generated,
wherein errors in the plurality of counts are detected and used to adjust at least one delay of the comparator clock signal to reduce the errors in the plurality of counts.

2. The circuit of claim 1 , wherein the at least one delay is adjusted when the one or more detected errors are above a threshold.

3. The circuit of claim 2 , wherein the at least one delay is adjusted across a plurality of iterations of providing the input signal pattern to the analog-to-digital converter to generate the plurality of counts, and wherein the at least one delay is incrementally increased on each iteration until the one or more detected errors are below the threshold.

4. The circuit of claim 1 , wherein the at least one delay is adjusted based on one or more of the detected errors.

5. The circuit of claim 4 , wherein the at least one delay is adjusted based on a difference between counts of two or more digital output codes.

6. The circuit of claim 4 , wherein the at least one delay is adjusted based on a count of a particular digital output code.

7. The circuit of claim 1 , wherein errors are detected in one or more predetermined digital output codes.

8. The circuit of claim 1 , wherein the calibration circuit adjusts at least one delay corresponding to a most significant bit produced by the analog-to-digital converter.

9. The circuit of claim 1 , wherein the calibration circuit adjusts a plurality of delays corresponding to multiple bits produced by the analog-to-digital converter.

10. The circuit of claim 1 , wherein different bits produced by the analog-to-digital converter use particular associated delays during normal operation.

11. The circuit of claim 1 , wherein the input signal pattern causes the analog-to-digital converter to produce all digital output codes across the range of analog input signal values.

12. The circuit of claim 1 , wherein the input signal pattern is a sine wave.

13. The circuit of claim 1 , wherein the input signal pattern corresponds to a pulse amplitude modulated (PAM) input signal.

14. The circuit of claim 1 , wherein the successive approximation register analog-to-digital converter comprises:
a digital-to-analog converter configured to receive a digital input signal and to provide a reference voltage to the comparator, the reference voltage having a value based on the digital input signal;
a clock circuit configured to generate a comparator clock signal;
a variable delay circuit coupled to the clock circuit to receive the comparator clock signal and configured to receive a delay control signal, the variable delay circuit generating a delayed clock signal having a delay based on the delay control signal; and
a digital circuit configured to provide the digital input signal to the digital-to-analog converter and the delay control signal to the variable delay circuit.

15. The circuit of claim 14 , wherein the digital-to-analog converter comprises a capacitive digital-to-analog converter.

16. The circuit of claim 1 , wherein the circuit comprises a plurality of said analog-to-digital converters each including the at least one comparator, and wherein the plurality of the analog-to-digital converters are configured in parallel.

17. The circuit of claim 1 , wherein the successive approximation register analog-to-digital converter comprises a plurality of comparators equal to a number of bits of the digital output code, and wherein the calibration circuit is configured to generate a separate delay control signal to adjust a separate delay of each of a plurality of comparator clock signals applied to the plurality of comparators.

18. The circuit of claim 1 , wherein the calibration circuit communicates with a calibration algorithm executing on a remote server, and wherein the calibration algorithm executing on the remote server detects errors in the plurality of counts and signals the calibration circuit to adjust the at least one delay.

19. A method of calibrating a successive approximation register analog-to-digital converter comprising:
providing an analog input signal pattern to an input of the successive approximation register analog-to-digital converter;
generating, by the successive approximation register analog-to-digital converter, a plurality of digital output codes representing the analog input signal pattern;
clocking at least one comparator in the successive approximation register analog-to-digital converter as part of generating the plurality of digital output codes;
generating a histogram of the digital output codes;
detecting errors in the digital output codes from the histogram; and
adjusting at least one delay of the clocking of the at least one comparator in response to the detected errors in the histogram.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Dyer Kenneth Colin
• Rankin John Paul

Classifications

• H03M1/125

  Asynchronous, i.e. free-running operation within each conversion cycle · CPC title

• H03M1/1009

  Calibration · CPC title

• H03M1/1033

  over the full range of the converter, e.g. for correcting differential non-linearity · CPC title

• H03M1/46 Primary

  with digital/analogue converter for supplying reference values to converter · CPC title

• H03M1/462 Primary

  Details of the control circuitry, e.g. of the successive approximation register · CPC title