Semiconductor device including data storage pattern

Patent metadata

Field	Value
Publication number	US-11387246-B2
Application number	US-202016890228-A
Country	US
Kind code	B2
Filing date	Jun 2, 2020
Priority date	Jun 17, 2019
Publication date	Jul 12, 2022
Grant date	Jul 12, 2022

Abstract

A semiconductor device includes a vertical pattern in a first direction, interlayer insulating layers, spaced apart, a side surface of each of the interlayer insulating layers facing a side of the vertical pattern, a gate electrode between the interlayer insulating layers, a side of the gate electrode facing the side of the vertical pattern, a dielectric structure between the vertical pattern and the interlayer insulating layers with the gate electrode between the interlayer insulating layers, and data storage patterns between the gate electrode and the vertical pattern, the data storage patterns spaced apart. The dielectric structure includes a first and a second dielectric layers, the second dielectric layer between the first dielectric layer and the vertical pattern. The data storage patterns are between the first dielectric layer and the second dielectric layer. The first dielectric layer includes portions between the data storage patterns and the gate electrode.

First claim

What is claimed is:

1. A semiconductor device comprising:
a vertical pattern extending in a first direction;
interlayer insulating layers, spaced apart from each other in the first direction, a side surface of each of the interlayer insulating layers facing a side surface of the vertical pattern;
a gate electrode between the interlayer insulating layers, a side surface of the gate electrode facing the side surface of the vertical pattern;
a dielectric structure between the vertical pattern and the interlayer insulating layers with the gate electrode between the interlayer insulating layers; and
a plurality of data storage patterns between the gate electrode and the vertical pattern, the plurality of data storage patterns spaced apart from each other in the first direction,
wherein
the dielectric structure includes a first dielectric layer and a second dielectric layer, the second dielectric layer between the first dielectric layer and the vertical pattern,
the plurality of data storage patterns are between the first dielectric layer and the second dielectric layer,
the first dielectric layer includes a plurality of portions, each portion between a respective each of the plurality of data storage patterns and the gate electrode, and the vertical pattern does not overlap the plurality of data storage patterns in the first direction, and
the second dielectric layer includes portions that overlap the first dielectric layer and the interlayer insulating layers in the first direction.

2. The semiconductor device of claim 1 , wherein the first dielectric layer extends from each portion along an upper surface and a lower surface of the respective each of the plurality of data storage patterns.

3. The semiconductor device of claim 2 , wherein the first dielectric layer extends from each portion, covering the upper surface and the lower surface of the respective each of the plurality of data storage patterns, in a direction away from a side surface of the gate electrode, the side surface facing the respective each of the plurality of data storage patterns.

4. The semiconductor device of claim 2 , wherein the first dielectric layer extends from each portion to between the interlayer insulating layers and the second dielectric layer.

5. The semiconductor device of claim 1 , further comprising:
a third dielectric layer covering a side surface of the gate electrode, the side surface facing a side surface of the vertical pattern, and the third dielectric layer between the gate electrode and the interlayer insulating layers.

6. The semiconductor device of claim 5 , wherein
the third dielectric layer includes a protrusion, the protrusion covering the side surface of the gate electrode and between the plurality of data storage patterns, and
the first dielectric layer is between each of the plurality of data storage patterns and the protrusion of the third dielectric layer and the first dielectric layer is between the second dielectric layer and the protrusion of the third dielectric layer.

7. The semiconductor device of claim 6 , further comprising:
an air gap in the protrusion of the third dielectric layer, the air gap defined by the third dielectric layer,
wherein at least a portion of the air gap is between the plurality of data storage patterns.

8. The semiconductor device of claim 1 , wherein the gate electrode includes first gate portions, the first gate portions adjacent to the interlayer insulating layers, and a second gate portion between the first gate portions, and
the first gate portions face the plurality of data storage patterns.

9. The semiconductor device of claim 8 , wherein each of the first gate portions includes a gate protrusion, the gate protrusion protruding further than the second gate portion in a direction of the vertical pattern.

10. The semiconductor device of claim 8 , wherein the second gate portion includes a gate protrusion protruding further than the first gate portions in the direction of the vertical pattern.

11. The semiconductor device of claim 8 , wherein a thickness of each of the first gate portions is different from a thickness of the second gate portion.

12. The semiconductor device of claim 11 , wherein the thickness of each of the first gate portions is greater than the thickness of the second gate portion.

13. The semiconductor device of claim 11 , wherein the thickness of each of the first gate portions is less than the thickness of the second gate portion.

14. The semiconductor device of claim 8 , further comprising:
a middle pattern between the second gate portion of the gate electrode and the dielectric structure,
wherein at least a portion of the middle pattern is between the plurality of data storage patterns.

15. The semiconductor device of claim 1 , further comprising a core pattern, wherein
each of the plurality of data storage patterns is a charge trap layer of a nonvolatile memory device,
the vertical pattern includes a semiconductor layer, and
the vertical pattern is between the core pattern and the second dielectric layer.

16. The semiconductor device of claim 1 , wherein the vertical pattern includes a plurality of protrusions, each protrusion extending in a direction to an adjacent one of the plurality of data storage patterns.

17. A semiconductor device comprising:
a substrate;
a vertical pattern on the substrate and extending n a first direction perpendicular to an upper surface of the substrate;
interlayer insulating layers, spaced apart from each other in the first direction, a side surface of each of the interlayer insulating layers facing a side surface of the vertical pattern;
a single gate electrode between the interlayer insulating layers, a side surface of the single gate electrode facing the side surface of the vertical pattern;
a dielectric structure between the vertical pattern and the interlayer insulating layers with the single gate electrode between the interlayer insulating layers; and
a plurality of data storage patterns between the single gate electrode and the vertical pattern in a second direction, the plurality of data storage patterns spaced apart from each other in the first direction,
wherein
the second direction is perpendicular to the first direction,
the single gate electrode includes a plurality of first gate portions and a second gate portion between the plurality of first gate portions,
the plurality of first gate portions face the plurality of data storage patterns,

each of the plurality of first gate portions includes a protrusion protruding further than the second gate portion in a direction of the vertical pattern, or the second gate portion includes a protrusion protruding further than the plurality of first gate portions in a direction of the vertical pattern
the plurality of data storage patterns include a lower data storage pattern and an upper data storage pattern on the lower data storage pattern, the single gate electrode includes a center portion between an upper surface and a lower surface of the single gate electrode,
an upper surface of the lower data storage pattern is at a lower level than the center portion of the single gate electrode and is at a higher level than the lower surface of the single gate electrode,
and a lower surface of the upper data storage pattern is at a higher level than the center portion of the single gate electrode and is at a lower level than the upper surface of the single gate electrode.

18. The semiconductor device of claim 17 , wherein the dielectric structure includes a first dielectric la

Assignees

• Samsung Electronics Co Ltd

Inventors

• Son Yonghoon

Classifications

• H10D30/68

  Floating-gate IGFETs · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D30/697

  having trapping at multiple separated sites, e.g. multi-particles trapping sites · CPC title

• H10D30/6893 Primary

  wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate · CPC title

• H01L27/1157 Primary

  Electricity · mapped topic