High-voltage shifter with reduced transistor degradation

Patent metadata

Field	Value
Publication number	US-11380401-B2
Application number	US-202117240358-A
Country	US
Kind code	B2
Filing date	Apr 26, 2021
Priority date	Jan 28, 2019
Publication date	Jul 5, 2022
Grant date	Jul 5, 2022

Abstract

Discussed herein are systems and methods for protecting against transistor degradation in a high-voltage (HV) shifter to transfer an input voltage to an access line, such as a global wordline. An embodiment of a memory device comprises memory cells and a HV shifter circuit that includes a signal transfer circuit, and first and second HV control circuits. The signal transfer circuit includes a P-channel transistor to transfer a high-voltage input to an access line. The first HV control circuit couples a bias voltage to the P-channel transistor for a first time period, and the second HV control circuit couples a stress-relief signal to the P-channel transistor for a second time period, after the first time period, to reduce degradation of the P-channel transistor. The transferred high voltage can be used to charge the access line to selectively read, program, or erase memory cells.

First claim

The invention claimed is:

1. A voltage shifter for transferring a high-voltage input to memory cells in a memory device, the voltage shifter comprising:
an input port to receive the high-voltage input;
an output port coupled to one or more of the memory cells via an access line;
a high-voltage transistor coupled between the input port and the output port; and
a transistor protection circuit, including at least one multiplexer configured to:
couple a bias voltage to the high-voltage transistor until a specific condition is satisfied; and
after satisfaction of the specific condition, decouple the bias voltage from the high-voltage transistor, and couple a stress-relief signal to the high-voltage transistor to protect the high-voltage transistor from degradation due to a gate-to-channel stress during the transferring of the high-voltage input from the input port to the output port.

2. The voltage shifter of claim 1 , wherein the specific condition includes expiration of a time period for coupling the bias voltage to the high-voltage transistor.

3. The voltage shifter of claim 1 , wherein the specific condition includes a monitored voltage at the output port satisfying a condition relative to the high-voltage input received at the input port.

4. The voltage shifter of claim 3 , wherein the specific condition includes the monitored voltage at the output port substantially reaching a value of the high-voltage input at the input port.

5. The voltage shifter of claim 1 , wherein the high-voltage transistor includes a first P-channel transistor or a first N-channel transistor.

6. The voltage shifter of claim 1 , wherein the high-voltage transistor includes a first P-channel transistor and a first N-channel transistor connected in series and coupled between the input port and the output port.

7. The voltage shifter of claim 1 , comprising a shifter selector circuit configured to couple a shifter enabling signal to an inverter to enable the voltage transfer from the input port to the output port in response to a first state of the shifter enabling signal, and to disable the voltage transfer in response to a different second state of the shifter enabling signal.

8. The voltage shifter of claim 7 , wherein the inverter includes a second P-channel transistor and a second N-channel transistor connected in parallel and coupled to the output port via a third N-channel transistor.

9. The voltage shifter of claim 1 , wherein the at least one multiplexer includes a first digital switch configured to:
switch to a first high-voltage source providing the bias voltage to the high-voltage transistor until the specific condition is satisfied; and
upon the satisfaction of the specific condition, decouple the bias voltage from, and couple a ground potential (Vss) to, the high-voltage transistor.

10. The voltage shifter of claim 9 , wherein the bias voltage has a value substantially equal to a supply voltage (Vcc).

11. The voltage shifter of claim 1 , wherein the at least one multiplexer includes a second digital switch configured to:
couple a ground potential (Vss) to the high-voltage transistor until the specific condition is satisfied; and
after a specified switching delay from the satisfaction of the specific condition, decouple the bias voltage from the high-voltage transistor, and switch to a second high-voltage source providing the stress-relief signal to the high-voltage transistor.

12. The voltage shifter of claim 11 , wherein the second high-voltage source has a voltage proportional to the high-voltage input.

13. The voltage shifter of claim 11 , wherein the at least one multiplexer includes a third digital switch configured to switch between a ground potential (Vss) and a third high-voltage source providing a control signal for controlling transfer of the stress-relief signal.

14. The voltage shifter of claim 1 , wherein the access line includes a word line or a global word line, and wherein the voltage shifter is configured to transfer the high-voltage input via the word line or the global word line to the one or more of the memory cells to perform a memory operation.

15. A memory device, comprising:
a group of memory cells; and
a voltage shifter circuit, including:
an input port;
an output port;
a high-voltage transistor coupled between the input port and the output port and configured to transfer a high-voltage input received at the input port to one or more access lines coupled between the output port and one or more of the group of memory cells, the transferred high-voltage input being applied to the one or more memory cells to perform a memory operation;
a transistor protection circuit including at least one multiplexer configured to couple a bias voltage to the high-voltage transistor until a specific condition is satisfied, and, after satisfaction of the specific condition, to decouple the bias voltage from the high-voltage transistor and couple a stress-relief signal to the high-voltage transistor to protect the high-voltage transistor from degradation due to a gate-to-channel stress during the transferring of the high-voltage input from the input port to the output port; and
a shifter control circuit configured to couple a shifter enabling signal to an inverter to enable the voltage transfer from the input port to the output port in response to a first state of the shifter enabling signal, and to disable the voltage transfer in response to a different second state of the shifter enabling signal.

16. The memory device of claim 15 , wherein the access line includes a word line or a global word line, and the voltage shifter is configured to use the transferred high-voltage input to perform the memory operation including programming, erasing, or reading one or more memory cells coupled to the word line or the global word line.

17. The memory device of claim 15 , wherein the high-voltage transistor includes a first P-channel transistor and a first N-channel transistor connected in series and coupled between the input port and the output port.

18. The memory device of claim 15 , wherein the inverter includes a second P-channel transistor and a second N-channel transistor connected in parallel and coupled to the output port via a third N-channel transistor.

19. The memory device of claim 15 , wherein the specific condition includes expiration of a time period for coupling the bias voltage to the high-voltage transistor.

20. The memory device of claim 15 , wherein the specific condition includes a monitored voltage at the output port satisfying a condition relative to the high-voltage input received at the input port.

Assignees

• Micron Technology Inc

Inventors

• Yamada Shigekazu

Classifications

• G11C5/08

  for interconnecting magnetic elements, e.g. toroidal cores · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C16/0408

  comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C16/107

  Programming all cells in an array, sector or block to the same state prior to flash erasing · CPC title