High-voltage shifter with reduced transistor degradation

Patent metadata

Field	Value
Publication number	US-10998050-B2
Application number	US-202016813273-A
Country	US
Kind code	B2
Filing date	Mar 9, 2020
Priority date	Jan 28, 2019
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

Discussed herein are systems and methods for protecting against transistor degradation in a high-voltage (HV) shifter to transfer an input voltage to an access line, such as a global wordline. An embodiment of a memory device comprises memory cells and a HV shifter circuit that includes a signal transfer circuit, and first and second HV control circuits. The signal transfer circuit includes a P-channel transistor to transfer a high-voltage input to an access line. The first HV control circuit couples a bias voltage to the P-channel transistor for a first time period, and the second HV control circuit couples a stress-relief signal to the P-channel transistor for a second time period, after the first time period, to reduce degradation of the P-channel transistor. The transferred high voltage can be used to charge the access line to selectively read, program, or erase memory cells.

First claim

The invention claimed is:

1. A memory device, comprising:
a group of memory cells; and
a high-voltage shifter circuit, including:
a signal transfer circuit, including a high-voltage transistor coupled between an input port and an output port of the high-voltage shifter circuit, the high-voltage transistor configured to transfer a high-voltage input received at the input port to an access line controllably coupled between the output port and one or more of the group of memory cells;
a first high-voltage control (HVC 1 ) circuit configured to controllably couple a bias voltage to the high-voltage transistor until a monitored condition is satisfied; and
a second high-voltage control (HVC 2 ) circuit configured to, in response to the satisfaction of the monitored condition, controllably couple a stress-relief signal to the high-voltage transistor to transfer the high-voltage input, for a specified time period.

2. The memory device of claim I. wherein the monitored condition includes a monitored voltage at the output port, and wherein a transition from an application of the bias voltage to an application of the stress-relief voltage occurs in response to determining a specified relationship between the monitored voltage at the output port relative to a value of the high-voltage input at the input port.

3. The memory device of claim 1 , wherein the HVC 1 circuit is configured to, in response to the satisfaction of the monitored condition, decouple the bias voltage from, and to couple to the ground potential (Vss) to, the high-voltage transistor.

4. The memory of device of claim 1 , wherein the HVC 2 circuit is configured to couple a ground potential (Vss) to the high-voltage transistor for a first time period until the monitored condition is satisfied.

5. The memory device of claim 1 , comprising a shifter selector circuit configured to couple a shifter enabling signal to an inverter to enable the voltage transfer from the input port to the output port in response to a first state of the shifter enabling signal, and to disable the voltage transfer in response to a different second state of the shifter enabling signal.

6. The memory device of claim 5 , wherein the inverter includes a second N-channel transistor and a second P-channel transistor connected in parallel and coupled to the output port of the high-voltage shifter circuit via a third N-channel transistor.

7. The memory device of claim 1 , wherein the HVC 1 circuit includes first digital switches configured to switch between a first high-voltage source and a ground potential (Vss) coupled to the high-voltage transistor.

8. The memory device of claim 1 , further comprising a high-voltage support (HVS) circuit configured to generate the stress-relief signal coupled to the high-voltage transistor.

9. The memory device of claim 8 , wherein the HVS circuit includes third digital switches configured to switch between a third high-voltage source and a ground potential (Vss).

10. The memory device of claim 9 , wherein the third high-voltage source has a voltage proportional to the high-voltage input.

11. The memory device of claim 9 , wherein the HVC 2 circuit includes second digital switches configured to switch between a second high-voltage source and a ground potential (Vss) to control the transfer of the stress-relief signal.

12. A memory device, comprising:
an NAND memory cell array; and
a charging circuit configured to apply a programming voltage to a word line (WL) or a global word line (GWL) controllably coupled to one or more memory cells of the NAND memory cell array, the charging circuit including a high-voltage shifter circuit that comprises:
a signal transfer circuit including a high-voltage transistor coupled between an input port and an output port of the high-voltage shifter circuit, the high-voltage transistor configured to transfer the programming voltage received at the input port to the WL or the GWL coupled to the output port;
a first high-voltage control (HVC 1 ) circuit configured to controllably couple a bias voltage to the high-voltage transistor until a monitored condition is satisfied; and
a second high-voltage control (HVC 2 ) circuit configured to, in response to the satisfaction of the monitored condition, controllably couple a stress-relief signal to the high-voltage transistor to transfer the programming voltage for a specified time period;

wherein the charging circuit is configured to apply the transferred programming voltage to the WL or the GWL to program the one or more memory cells coupled to the WL or the GWL.

13. The memory device of claim 12 , wherein the monitored condition includes a monitored voltage at the output port, and wherein a transition from an application of the bias voltage to an application of the stress-relief voltage occurs in response to determining a specified relationship between the monitored voltage at the output port relative to a value of the high-voltage input at the input port.

14. The memory device of claim 12 , wherein the high-voltage shifter includes a shifter selector circuit configured to couple a shifter enabling signal to an inverter to enable the voltage transfer from the input port to the output port in response to a first state of the shifter enabling signal, and to disable the voltage transfer in response to a different second state of the shifter enabling signal.

15. The memory device of claim 14 , wherein the inverter includes a second N-channel transistor and a second P-channel transistor connected in parallel and coupled to the output port of the high-voltage shifter circuit via a third N-channel transistor.

16. The memory device of claim 12 , wherein the high-voltage shifter includes a high-voltage support (HVS) circuit including third digital switches configured to switch between a third high-voltage source and a ground potential (Vss), the HVS circuit configured to generate the stress-relief signal coupled to the high-voltage transistor.

17. A memory device, comprising:
a group of memory cells access through use of multiple access lines respectively coupled to multiple memory cells of the group of memory cells; and
a high-voltage shifter circuit, including:
a high-voltage transistor coupled between an input port and an output port of the high-voltage shifter circuit, the high-voltage transistor configured to transfer a high-voltage input received at the input port to an access line coupled between the output port and one or more of the group of memory cells;
a control circuit configured to controllably couple a bias voltage to the high-voltage transistor until a monitored condition is satisfied, and in response to the satisfaction of the monitored condition, controllably couple a stress-relief signal to the high-voltage transistor to transfer the high-voltage input to the high voltage output port.

18. The memory device of claim 17 , comprising a shifter selector circuit configured to couple a shifter enabling signal to an inverter to enable the voltage transfer from the input port to the output port in response to a first state of the shifter enabling signal, and to disable the voltage transfer in response to a different second state of the shifter enabling signal.

19. A memory device, comprising:
a group of memory cells; and
a control circuit configured to:
couple a bias voltage to a high-voltage transistor that is coupled between an input port and an output port of the high-voltage shifter circuit until a monitored condition is satisfied;
in response to the satisfaction of the monitored conditi

Assignees

• Micron Technology Inc

Inventors

• Yamada Shigekazu

Classifications

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C16/0466

  comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C16/0408

  comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title