Method for manufacturing semiconductor structure and planarization process thereof

Patent metadata

Field	Value
Publication number	US-11377347-B2
Application number	US-202016917901-A
Country	US
Kind code	B2
Filing date	Jul 1, 2020
Priority date	May 18, 2020
Publication date	Jul 5, 2022
Grant date	Jul 5, 2022

Abstract

A method for manufacturing semiconductor structure includes: providing a substrate having a first surface; forming a trench on the first surface, wherein a bottom surface and side walls of the substrate are configured along an outer periphery of the trench; annealing the substrate with high-purity argon or high-purity hydrogen to flatten the bottom surface and the side walls; conformally disposing a composite-material layer to cover the first surface, the bottom surface and the side walls; disposing a polysilicon material layer in the trench; removing the composite-material layer on the first surface; forming a multi-layer metal interconnection structure on the first surface and the polysilicon material layer, the multi-layer metal interconnection structure including a MEMS frame structure and through holes; removing the polysilicon material layer and the composite-material layer; using plasma treatment to the trench to flatten the bottom surface and the side walls. The plasma contains inert gas and hydrogen.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor structure, comprising steps of:
providing a substrate having a first surface;
forming at least one trench on the first surface of the substrate, wherein a bottom surface and a plurality of side walls of the substrate are configured along an outer periphery of the at least one trench;
performing a first planarization process comprising annealing the substrate with the at least one trench thereon in an annealing ambient comprising a gas selected from one of argon and hydrogen to flatten at least one of the bottom surface and the side walls of the at least one trench;
conformally disposing a composite-material layer to cover the first surface of the substrate, the bottom surface and the side walls of the at least one trench;
disposing a polysilicon material layer in the at least one trench, wherein the polysilicon material layer covers the composite-material layer on the bottom surface and the side walls;
removing the composite-material layer on the first surface;
forming a multilayer metal interconnection structure on the first surface and the polysilicon material layer, wherein the multilayer metal interconnection structure comprises a micro-electromechanical system (MEMS) frame structure and a plurality of through holes;
removing the polysilicon material layer and the composite-material layer in the at least one trench; and
performing a second planarization process, in which a plasma treatment is used to process the at least one trench to flatten the bottom surface and the side walls thereof, wherein the plasma treatment comprises a plasma comprising inert gas and hydrogen.

2. The method for manufacturing the semiconductor structure according to claim 1 , wherein the step of conformally disposing the composite-material layer comprises steps of:
conformally forming a liner oxide layer to cover the first surface of the substrate and the bottom surface and the side walls of the at least one trench; and
conformally forming a passivation layer on the liner oxide layer.

3. The method for manufacturing the semiconductor structure according to claim 1 , wherein during the first planarization process, the annealing ambient comprises argon and an anneal temperature is between 750° C. and 1100° C.

4. The method for manufacturing the semiconductor structure according to claim 1 , wherein during the first planarization process, the annealing ambient comprises hydrogen and an anneal temperature is between 750° C. and 1100° C.

5. The method for manufacturing the semiconductor structure according to claim 1 , wherein during the second planarization process, a temperature of the plasma treatment is between 300° C. and 400° C.

6. The method for manufacturing the semiconductor structure according to claim 1 , wherein a content of hydrogen in the plasma is between 2.5% and 10%, and a content of inert gas is between 90% and 97.5%.

7. The method for manufacturing the semiconductor structure according to claim 1 , wherein after disposing the polysilicon material layer in the at least one trench, a polishing process is performed to make a top surface of the polysilicon material layer and the composite-material layer be at the same height.

8. The method for manufacturing the semiconductor structure according to claim 1 , wherein before or after removing the composite-material layer on the first surface, a portion of the polysilicon material layer is removed by an etching back process to make a top surface of the polysilicon material layer and the first surface of the substrate be at the same height.

9. The method for manufacturing the semiconductor structure according to claim 1 , wherein the MEMS frame structure corresponds to a position of the at least one trench, and some of the plurality of through holes communicate with the at least one trench.

Assignees

• United Microelectronics Corp

Inventors

• Li Xiang
• Chen Ding Lung

Classifications

• H10P95/906 Primary

  for altering the shape of semiconductors, e.g. smoothing the surface · CPC title

• B81C2201/0126

  Processes for the planarization of structures not provided for in B81C2201/0119 - B81C2201/0125 · CPC title

• B81C1/00611 Primary

  Processes for the planarisation of structures (planarising depositions C23C, H10) · CPC title

• B81B2203/033

  Trenches · CPC title

• B81C2201/0123

  Selective removal · CPC title