Method of forming ultra-smooth bottom electrode surface for depositing magnetic tunnel junctions

Patent metadata

Field	Value
Publication number	US-11374165-B2
Application number	US-202016810697-A
Country	US
Kind code	B2
Filing date	Mar 5, 2020
Priority date	Oct 14, 2016
Publication date	Jun 28, 2022
Grant date	Jun 28, 2022

Abstract

A process sequence is provided to provide an ultra-smooth (0.2 nm or less) bottom electrode surface for depositing magnetic tunnel junctions thereon. In one embodiment, the sequence includes forming a bottom electrode pad through bulk layer deposition followed by patterning and etching. Oxide is then deposited over the formed bottom electrode pads and polished back to expose the bottom electrode pads. A bottom electrode buff layer is then deposited thereover following a pre-clean operation. The bottom electrode buff layer is then exposed to a chemical mechanical polishing process to improve surface roughness. An magnetic tunnel junction deposition is then performed over the bottom electrode buff layer.

First claim

The invention claimed is:

1. A structure, comprising:
a substrate having a plurality of conductive vias thereon;
a plurality of bottom electrode pads disposed over the plurality of conductive vias;
a dielectric material disposed between the plurality of bottom electrode pads;
a bottom electrode buff layer comprising tantalum nitride is disposed over the plurality of bottom electrode pads and the dielectric material; and
a plurality of magnetic tunnel junction (MTJ) structures disposed over one or more of the plurality of bottom electrode pads.

2. The structure of claim 1 , wherein a surface roughness of the bottom electrode buff layer is less than 0.2 nm.

3. The structure of claim 1 , wherein a thickness of the bottom electrode buff layer is about 2 nm to about 10 nm.

4. The structure of claim 1 , wherein a size of at least one of the MTJ structures is less than a size of at least one of the bottom electrode pads.

5. The structure of claim 1 , wherein a size of at least one of the MTJ structures is greater than a size of at least one of the bottom electrode pads.

6. The structure of claim 1 , wherein a size of at least one of the MTJ structures is equal to a size of at least one of the bottom electrode pads.

7. The structure of claim 1 , wherein the tantalum nitride of the bottom electrode buff layer has a resistance of about 6 ohms/sq to about 7 ohms/sq.

8. The structure of claim 1 , wherein a size of at least one of the bottom electrode pads is less than, equal to, or greater than a size of at least one of the conductive vias.

9. A structure, comprising:
a substrate having a plurality of conductive vias thereon;
a plurality of bottom electrode pads disposed over the plurality of conductive vias;
a dielectric material disposed between the plurality of bottom electrode pads;
a bottom electrode buff layer comprising tantalum nitride is disposed over the plurality of bottom electrode pads and the dielectric material; and
a plurality of magnetic tunnel junction (MTJ) structures disposed over one or more of the plurality of bottom electrode pads, wherein a size of at least one of the MTJ structures is less than a size of at least one of the bottom electrode pads and a size of at least one of the MTJ structures is greater than a size of at least one of the bottom electrode pads.

10. The structure of claim 9 , wherein a surface roughness of the bottom electrode buff layer is less than 0.2 nm.

11. The structure of claim 9 , wherein a thickness of the bottom electrode buff layer is about 2 nm to about 10 nm.

12. The structure of claim 9 , wherein the tantalum nitride of the bottom electrode buff layer has a resistance of about 6 ohms/sg to about 7 ohms/sq.

13. The structure of claim 9 , wherein a size of at least one of the plurality of bottom electrode pads is less than, equal to, or greater than a size of at least one of the plurality of conductive vias.

14. The structure of claim 9 , wherein the plurality of bottom electrode pads comprises tantalum, tantalum nitride, tungsten, tungsten nitride, or combinations thereof.

15. A structure, comprising:
a substrate having a plurality of conductive vias thereon;
a first bottom electrode pad disposed over at least one of the plurality of conductive vias;
a second bottom electrode pad disposed over at least one of the plurality of conductive vias;
a dielectric material disposed between the first bottom electrode pad and the second bottom electrode pad;
a bottom electrode buff layer comprising tantalum nitride is disposed over the first bottom electrode pad, the second bottom electrode pad, and the dielectric material;
a first magnetic tunnel junction (MTJ) structure disposed over the first bottom electrode pad, wherein the first MTJ structure size is larger than a size of the first bottom pad; and
a second MTJ structure disposed over the second bottom electrode pad, wherein the second MTJ structure size is smaller than a size of the second bottom electrode pad.

16. The structure of claim 15 , wherein a surface roughness of the bottom electrode buff layer is less than 0.2 nm.

17. The structure of claim 15 , wherein a thickness of the bottom electrode buff layer is about 2 nm to about 10 nm.

18. The structure of claim 15 , wherein the tantalum nitride of the bottom electrode buff layer has a resistance of about 6 ohms/sq to about 7 ohms/sq.

19. The structure of claim 15 , wherein a size of at least one of the first bottom electrode pad or the second bottom electrode pad is less than, equal to, or greater than a size of at least one of the plurality of conductive vias.

20. The structure of claim 15 , wherein each of the first and second bottom electrode pads independently comprises tantalum, tantalum nitride, tungsten, tungsten nitride, or combinations thereof.

Assignees

• Applied Materials Inc

Inventors

• Xue Lin
• Hassan Sajjad Amin
• Pakala Mahendra
• Ahn Jaesoo

Classifications

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title

• H10B61/00 Primary

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title

• H10N50/10 Primary

  Magnetoresistive devices · CPC title

• H01L27/222

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic