Microelectronic assembly from processed substrate

Patent metadata

Field	Value
Publication number	US-11367652-B2
Application number	US-202016842233-A
Country	US
Kind code	B2
Filing date	Apr 7, 2020
Priority date	Dec 28, 2016
Publication date	Jun 21, 2022
Grant date	Jun 21, 2022

Abstract

Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.

First claim

What is claimed is:

1. A method comprising:
providing a substrate having a surface with a generally planarized region and conductive material in one or more cavities disposed within a recessed region of the surface; and
forming one or more conductive interconnect structures from the conductive material within the one or more cavities such that a preselected portion of the one or more interconnect structures protrudes from the one or more cavities into the recessed region and extends above a surface of the recessed region surrounding the one or more cavities.

2. The method of claim 1 , wherein the substrate is a first substrate, the one or more cavities are one or more first cavities, and the one or more interconnect structures are one or more first interconnect structures, the method further comprising:
providing a second substrate having a generally planarized region and conductive material in one or more second cavities extending a preselected depth below a surface of the second substrate;
bonding the generally planarized region of the second substrate to the generally planarized region of the first substrate, the recessed region of the first substrate and the surface of the second substrate forming a gap; and
bonding the one or more second interconnect structures to the one or more first interconnect structures of the first substrate.

3. The method of claim 2 , wherein at least one of the one or more first interconnect structures protrudes above the surface of the first substrate or at least one of the one or more second interconnect structures protrudes above the surface of the second substrate.

4. The method of claim 2 , wherein the recessed region is a first recessed region, the method further comprising forming a second recessed region in the surface of the second substrate extending a preselected depth below the surface of the second substrate, such that the second recessed region surrounds the one or more second cavities and the one or more second interconnect structures, and such that a preselected portion of the one or more second interconnect structures protrudes from the one or more second cavities above a surface of the second recessed region; and
wherein, after bonding, the first recessed region of the first substrate overlaps the second recessed region of the second substrate.

5. The method of claim 4 , wherein at least one of the first recessed region and the second recessed region includes multiple interconnect structures disposed therein.

6. The method of claim 2 , further comprising forming one or more third interconnect structures extending through the first substrate and one or more corresponding fourth interconnect structures extending through the second substrate, the one or more third and fourth interconnect structures disposed outside of the recessed region of the first substrate; and
bonding the one or more third interconnect structures to the one or more fourth interconnect structures.

7. The method of claim 2 , further comprising bonding the generally planarized region of the second substrate to the generally planarized region of the first substrate, and bonding the one or more second interconnect structures to the one or more first interconnect structures of the first substrate, using a direct bonding technique without an intervening material.

8. The method of claim 1 , wherein the substrate is a first substrate, the method further comprising:
providing a second substrate having a void through the second substrate;
bonding the second substrate to the surface of the first substrate with the void of the second substrate disposed over the recessed region of the first substrate; and
coupling a membrane to the second substrate, over the void of the second substrate and over the one or more interconnect structures of the first substrate.

9. The method of claim 8 , further comprising forming a micro electro-mechanical (MEMS) device from at least the bonding and the coupling.

10. The method of claim 8 , further comprising forming one or more third interconnect structures extending through the first substrate, and one or more corresponding fourth interconnect structures extending through the second substrate, the one or more third and fourth interconnect structures disposed outside of the recessed region of the first substrate; and
bonding the one or more third interconnect structures to the one or more fourth interconnect structures.

11. The method of claim 1 , wherein the substrate is a first substrate, the method further comprising:
providing a second substrate that is permeable to one or both of a predefined light spectrum and one or more predefined fluids; and
bonding the second substrate to the surface of the first substrate such that the second substrate covers the recessed region of the first substrate and the one or more interconnect structures of the first substrate.

12. The method of claim 1 , wherein the substrate is a first substrate, the method further comprising:
providing a second substrate that is impermeable to one or more predefined fluids; and
bonding the second substrate to the surface of the first substrate such that the second substrate covers the recessed region of the first substrate and the one or more interconnect structures of the first substrate.

13. The method of claim 1 , further comprising selectively etching the one or more interconnect structures or selectively etching the surface of the substrate, such that the one or more interconnect structures have a variance in surface topology of less than 2 nanometers after the selective etching of the one or more interconnect structures or after the selective etching of the surface of the substrate.

14. A method comprising:
providing a substrate having a surface with a generally planarized region and one or more cavities disposed in the surface;
filling the one or more cavities with a conductive material;
selectively etching the surface until a preselected portion of the conductive material protrudes above the surface, forming one or more interconnect structures, and smoothing a surface topology of the surface;
selectively etching a predetermined amount of conductive material from the one or more interconnect structures, and smoothing a surface topology of the one or more interconnect structures; and
bonding a microelectronic component having a smooth surface topology to the surface.

15. The method of claim 14 , wherein the microelectronic component has one or more conductive features to the surface; and
further comprising interconnecting and electrically coupling one or more of the interconnect structures to the one or more conductive features of the microelectronic component.

16. The method of claim 14 , wherein the selectively etching the surface comprises etching with a first selective etchant for a preselected duration, the first selective etchant comprising: glycerated diluted hydrofluoric acid or buffered hydrofluoric acid, organic acid, and deionized water, with or without a stabilizing additive.

17. The method of claim 14 , wherein the selectively etching the predetermined amount of conductive material from the one or more interconnect structures comprises etching with a second selective etchant for a preselected duration, the second selective etchant comprising: one or more oxidizing agents, one or more organic acids, and glycerol, wherein the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary.

18. The method of claim 14 , wherein the bonding the microelectronic component to the surf

Assignees

• Invensas Bonding Tech Inc

Inventors

• Uzoh Cyprian Emeka
• Mirkarimi Laura Wills

Classifications

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/934

  Cross-sectional shape, i.e. in side view · CPC title

• H10W90/00

  Package configurations · CPC title