Semiconductor material having tunable permittivity and tunable thermal conductivity

Patent metadata

Field	Value
Publication number	US-11355340-B2
Application number	US-202016742827-A
Country	US
Kind code	B2
Filing date	Jan 14, 2020
Priority date	Jul 19, 2019
Publication date	Jun 7, 2022
Grant date	Jun 7, 2022

Abstract

A layered structure for semiconductor application is described herein. The layered structure includes a starting material and a fully depleted porous layer formed over the starting material with high resistivity. In some embodiments, the layered structure further includes epitaxial layer grown over the fully depleted porous layer. Additionally, a process of making the layered structure including forming the fully depleted porous layer and epitaxial layer grown over the porous layer is described herein.

First claim

What is claimed is:

1. A layered structure comprising:
a starting material layer; and
a fully depleted porous layer over the starting material layer,
wherein a first band gap of the fully depleted porous layer is greater than a second band gap of the starting material layer and the fully depleted porous layer is elementally identical to the starting material layer,
wherein the fully depleted porous layer comprises a first porosity in a first region and a second porosity in a second region, and
wherein the first and second regions are adjacent to each other in a horizontal direction.

2. The layered structure of claim 1 , wherein the fully depleted porous layer is between 10-20 μm thick with resistivity greater than 10000 ohm-cm.

3. The layered structure of claim 1 , wherein the starting material layer comprises silicon.

4. The layered structure of claim 1 , wherein the starting material layer comprises a material having resistivity in a range of 0.1 to 10 ohm-cm.

5. The layered structure of claim 1 , wherein the starting material layer comprises a plurality of layers stacked vertically, wherein a resistivity of the plurality of layers of the starting material layer varies.

6. The layered structure of claim 1 , wherein the starting material layer is a silicon substrate with a <111> or <100> crystal orientation.

7. The layered structure of claim 1 , wherein the fully depleted porous layer is lattice matched to the starting material layer.

8. The layered structure of claim 1 , wherein the first region of the fully depleted porous layer comprises a plurality of sublayers stacked vertically, wherein a porosity of the plurality of sublayers is graded with a sublayer with a low porosity at a surface of the first region of the fully depleted porous layer, and a sublayer with a high porosity at an interface of the first region of the fully depleted porous layer and the starting material layer.

9. The layered structure of claim 1 , wherein the first region of the fully depleted porous layer comprises a plurality of sublayers stacked vertically, wherein a porosity of the plurality of sublayers is graded with a sublayer with a high porosity at a surface of the first region of the fully depleted porous layer, and a sublayer with a low porosity at an interface of the first region of the fully depleted porous layer and the starting material layer.

10. The layered structure of claim 1 , wherein the first region of the fully depleted porous layer comprises periodically alternating vertical sublayers of the first porosity and a third porosity.

11. The layered structure of claim 10 , wherein the first porosity is a high porosity, and the third porosity is a low porosity.

12. The layered structure of claim 10 , wherein the periodically alternating vertical sublayers of the first porosity and the third porosity form an acoustic reflector.

13. The layered structure of claim 10 , wherein the periodically alternating vertical sublayers of the first porosity and the third porosity form a coherent phonon structure.

14. The layered structure of claim 1 , wherein thermal conductivity of the layered structure is at least equal to 3 W/mK.

15. The layered structure of claim 1 , wherein permittivity of the layered structure is in a range of approximately 2 to 4 farads per meter.

16. A layered structure comprising:
a starting material layer;
a fully depleted porous layer over the starting material layer, wherein a first band gap of the fully depleted porous layer is greater than a second band gap of the starting material layer and the fully depleted porous layer is elementally identical to the starting material layer; and
an epitaxial layer grown over the fully depleted porous layer,
wherein the fully depleted porous layer comprises a first porosity in a first region and a second porosity in a second region, and
wherein the first and second regions are adjacent to each other in a horizontal direction.

17. The layered structure of claim 16 , wherein the epitaxial layer is a silicon semiconductor layer.

18. The layered structure of claim 16 , wherein the epitaxial layer is selected from the group consisting of a InP layer, a cREO layer, a Mo layer, a AlGaInN layer, a RE-III-N layer and a metal layer.

19. The layered structure of claim 16 , wherein the layered structure is a layer of an RF switch structure.

20. The layered structure of claim 16 , wherein the layered structure is a layer of an integrated passive device.

21. The layered structure of claim 16 , wherein the layered structure is a layer in an RF filter.

22. The layered structure of claim 16 , wherein the starting material layer comprises a first region having a first resistivity and a second region having a second resistivity.

23. The layered structure of claim 22 , wherein:
the fully depleted porous layer is formed over the first region; and
the layered structure further comprises a non-fully depleted porous layer formed over the second region.

24. The layered structure of claim 16 , wherein the starting material layer is a silicon substrate with a <111> or <100> crystal orientation.

25. A method of forming a layered structure, the method comprising:
forming a fully depleted porous layer from a starting material,
wherein a first band gap of the fully depleted porous layer is greater than a second band gap of the starting material and the fully depleted porous layer is elementally identical to the starting material, and
wherein the fully depleted porous layer comprises a first porosity in a first region and a second porosity in a second region, and
wherein the first and second regions are adjacent to each other in a horizontal direction.

26. The method of claim 25 , wherein the starting material is a p-type, boron doped substrate having a resistivity in the range of 0.1 to 10 ohm-cm.

27. The method of claim 25 , further comprising:
growing an epitaxial layer over the fully depleted porous layer.

28. The method of claim 25 , wherein the starting material is a silicon substrate with a <111> or <100> crystal orientation.

Assignees

• Iqe Plc

Inventors

• Hammond Richard
• Nelson Drew
• Gott Alan
• Pelzel Rodney
• Clark Andrew

Classifications

• H10P14/3256

  Microstructure · CPC title

• H10P90/00 Primary

  Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement · CPC title

• H10P50/613

  of Group IV materials · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P14/6349

  Deposition of epitaxial materials · CPC title