Adaptive error amplifier clamping in a multi-feedback loop system

US11349391B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-11349391-B1
Application numberUS-202017106837-A
CountryUS
Kind codeB1
Filing dateNov 30, 2020
Priority dateNov 30, 2020
Publication dateMay 31, 2022
Grant dateMay 31, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present document relates to power converters with multiple feedback loops. The present document relates to a power converter with at least two feedback loops. The power converter may include a first error amplifier configured to generate a first error signal based on a first reference signal and a first feedback signal. The power converter may include a second error amplifier configured to generate a second error signal based on a second reference signal and a second feedback signal. The power converter may include a selector circuit configured to generate a selection signal by selecting the first error signal or the second error signal. The power converter may include a first clamp circuit configured to limit the first error signal to a first threshold value. The power converter may include a first threshold value generator circuit configured to generate the first threshold value dependent on the first error signal.

First claim

Opening claim text (preview).

What is claimed is: 1. A power converter comprising a first error amplifier configured to generate a first error signal based on a first reference signal and a first feedback signal, a second error amplifier configured to generate a second error signal based on a second reference signal and a second feedback signal, a selector circuit configured to generate a selection signal by selecting the first error signal or the second error signal, a first clamp circuit configured to limit the first error signal to a first threshold value, and a first threshold value generator circuit configured to generate the first threshold value dependent on the first error signal, wherein the selector circuit is a maximum selector circuit configured to generate the selection signal by selecting the larger one of the first error signal and the second error signal, and wherein the first clamp circuit is a lower clamp circuit configured to limit the first error signal such that the first error signal does not fall below the first threshold voltage. 2. The power converter according to claim 1 , wherein the first threshold value generator circuit is configured to generate the first threshold value such that the first threshold value increases when the first error signal increases. 3. The power converter according to claim 1 , further comprising a modulator circuit configured to generate, based on the selection signal, one or more control signals for controlling a power stage of the power converter. 4. The power converter according to claim 1 , further comprising a high-side switching element, a low-side switching element, and an inductor, wherein the high-side switching element is coupled to a switching node, the low-side switching element is coupled between the switching node and a reference potential, and the inductor is coupled to the switching node. 5. A method of operating a power converter, wherein the method comprises generating a first error signal based on a first reference signal and a first feedback signal, generating a second error signal based on a second reference signal and a second feedback signal, generating a selection signal by selecting the first error signal or the second error signal, limiting the first error signal to a first threshold value, and generating the first threshold value dependent on the first error signal, wherein a selector circuit is a maximum selector circuit, wherein a first clamp circuit is a lower clamp circuit, and wherein the method comprises generating, by the maximum selector circuit, the selection signal by selecting the larger one of the first error signal and the second error signal, and limiting, by the lower clamp circuit, the first error signal such that the first error signal does not fall below the first threshold voltage. 6. The method according to claim 5 , comprising generating the first threshold value such that the first threshold value increases when the first error signal increases. 7. The method according to claim 5 , further comprising generating, based on the selection signal, one or more control signals for controlling a power stage of the power converter. 8. The method according to claim 5 , wherein the power converter further comprises a high-side switching element, a low-side switching element, and an inductor, and wherein the method comprises coupling the high-side switching element to a switching node, coupling the low-side switching element between the switching node and a reference potential, and coupling the inductor to the switching node. 9. A power converter comprising a first error amplifier configured to generate a first error signal based on a first reference signal and a first feedback signal, a second error amplifier configured to generate a second error signal based on a second reference signal and a second feedback signal, a selector circuit configured to generate a selection signal by selecting the first error signal or the second error signal, a first clamp circuit configured to limit the first error signal to a first threshold value, and a first threshold value generator circuit configured to generate the first threshold value dependent on the first error signal, wherein the first error signal is a first error current, and wherein the first threshold value generator circuit comprises a current mirror configured to generate a mirror current based on the first error current, and a resistive element configured to translate said mirror current into the first threshold value. 10. The power converter according to claim 9 , wherein the resistive element is coupled between an output of the selector circuit and the first clamp circuit. 11. The power converter according to claim 9 , further comprising an additional reference current source coupled to said resistive element. 12. The power converter according to claim 9 , wherein the current mirror is connected to said resistive element such that the mirror current flows through said resistive element and generates a voltage difference between the output of the selector circuit and the first clamp circuit. 13. The power converter according to claim 9 , wherein the first clamp circuit is an upper clamp circuit configured to limit the first error signal such that the first error signal does not exceed the first threshold voltage. 14. The power converter according to claim 9 , wherein the selector circuit is a minimum selector circuit configured to generate the selection signal by selecting the smaller one of the first error signal and the second error signal. 15. A power converter comprising a first error amplifier configured to generate a first error signal based on a first reference signal and a first feedback signal, a second error amplifier configured to generate a second error signal based on a second reference signal and a second feedback signal, a selector circuit configured to generate a selection signal by selecting the first error signal or the second error signal, a first clamp circuit configured to limit the first error signal to a first threshold value, and a first threshold value generator circuit configured to generate the first threshold value dependent on the first error signal, wherein the first threshold value generator circuit is configured to generate the first threshold value such that the first threshold value is proportional to the first error signal, wherein the selector circuit comprises a unity gain amplifier, and wherein the first error signal is applied to a first non-inverting input of the unity gain amplifier, the second error signal is applied to a second non-inverting input of the unity gain amplifier, and an output signal of the unity gain amplifier is feedback to an inverting input of the unity gain amplifier. 16. A power converter comprising a first error amplifier configured to generate a first error signal based on a first reference signal and a first feedback signal, a second error amplifier configured to generate a second error signal based on a second reference signal and a second feedback signal, a selector circuit configured to generate a selection signal by selecting the first error signal or the second error signal, a first clamp circuit configured to limit the first error signal to a first threshold value, and a first threshold value generator circuit configured to generate the first threshold value dependent on the first error signal, wherein the first threshold value generator circuit is configured to generate the first threshold value such that the first threshold v

Assignees

Inventors

Classifications

  • H02M3/1584Primary

    with a plurality of power processing stages connected in parallel · CPC title

  • with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation · CPC title

  • the disturbance parameters being input voltage fluctuations · CPC title

  • Arrangements for modifying reference values, feedback values or error values in the control loop of a converter · CPC title

  • H02M3/155Primary

    using semiconductor devices only · CPC title

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What does patent US11349391B1 cover?
The present document relates to power converters with multiple feedback loops. The present document relates to a power converter with at least two feedback loops. The power converter may include a first error amplifier configured to generate a first error signal based on a first reference signal and a first feedback signal. The power converter may include a second error amplifier configured to …
Who is the assignee on this patent?
Dialog Semiconductor Uk Ltd
What technology area does this patent fall under?
Primary CPC classification H02M3/1584. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 31 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).