Multi-level buck converter with current limit and 50% duty cycle control

Patent metadata

Field	Value
Publication number	US-10554124-B1
Application number	US-201816149024-A
Country	US
Kind code	B1
Filing date	Oct 1, 2018
Priority date	Oct 1, 2018
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

A multi-level buck converter is provided with multiple control loops to regulate the output voltage in the presence of over-current conditions and in the vicinity of a 50% duty cycle.

First claim

What is claimed is:

1. A method for a multi-level buck converter, comprising:
responsive to a first comparison of an error signal to a dual-ramp signal, selecting for a first switching state by switching on a first plurality of switches arranged in series between an input voltage node and an inductor switching node and by switching off a second plurality of switches arranged in series between the inductor switching node and ground;
determining whether a duration for the first switching state equals a minimum pulse width responsive to an output voltage for the multi-level buck converter being substantially 50% of an input voltage for the multi-level buck converter;
selecting for a second switching state following a termination of the first switching state by switching off the first plurality of switches and by switching on the second plurality of switches responsive to a determination that the duration for the first switching state equals the minimum pulse width; and
terminating the second switching state so that a duration of the second switching state equals the minimum pulse width.

2. The method of claim 1 , further comprising:
responsive to a second comparison of the error signal to the dual-ramp signal, selecting for a repeat of the second switching state by again switching off the first plurality of switches and by switching on the second plurality of switches;
determining whether a duration for the repeat of the second switching state equals the minimum pulse width;
selecting for a repeat of the first switching state following a termination of the repeat of the second switching state by again switching on the first plurality of switches and by switching off the second plurality of switches responsive to a determination that the duration for the repeat of the first switching state equals the minimum pulse width; and
terminating the repeat of the first switching state so that the repeat of the first switching state has a duration equaling the minimum pulse width.

3. The method of claim 1 , further comprising:
prior to the first switching state, selecting for a third switching state in which a flying capacitor is charged; and
following the second switching state, selecting for a fourth switching state in which the flying capacitor is discharged.

4. The method of claim 3 , wherein the flying capacitor floats during the first switching state and during the second switching state.

5. The method of claim 1 , further comprising:
adjusting the minimum pulse width.

6. A multi-level buck converter, comprising:
a first plurality of switches arranged in series between a voltage input node and an inductor switching node;
a second plurality of switches arranged in series between the inductor switching node and ground;
a dual-ramp generator configured to generate a dual-ramp signal;
an error amplifier configured to drive an error signal responsive to a difference between an output voltage for the multi-level buck converter and a reference voltage; and
a controller configured to:
select for a first switching state in which both the first plurality of switches are all on and in which the second plurality of switches are all off for a minimum pulse width responsive to a first comparison of the error signal to the dual-ramp signal and responsive to the output voltage for the multi-level buck converter being substantially 50% of an input voltage for the multi-level buck converter; and
select for a second switching state following the first switching state, wherein both the first plurality of switches are all off and the second plurality of switches are all on for the minimum pulse width following a termination of the first switching state.

7. The multi-level buck converter of claim 6 , wherein the controller is further configured to:
select for a repeat of the second switching state for a duration equaling the minimum pulse width responsive to a second comparison of the error signal to the dual-ramp signal; and
select for a repeat of the first switching state for a first duration following a termination of the repeat of the first switching state.

8. The multi-level buck converter of claim 7 , wherein the first duration equals the minimum pulse width.

9. The multi-level buck converter of claim 6 , wherein the first plurality of switches is a first pair of switches, and wherein the second plurality of switches is a second pair of switches.

10. A method for a multi-level buck converter, comprising:
generating a first error signal responsive to a difference between an output voltage for the multi-level buck converter and a first reference voltage;
selecting from a plurality of four switching configurations for a plurality of switches for the multi-level buck converter responsive to a comparison of the first error signal to a dual-ramp signal;
determining whether an over-current condition occurred during a magnetizing one of the plurality of four switching configurations;
clamping the first error signal to a reduced level responsive to the determination of the over-current condition during the magnetizing one of the plurality of four switching configurations;
generating a second error signal responsive to a difference between a flying capacitor voltage for the multi-level buck converter and a second reference voltage;
asserting a first control signal at a beginning of each period for a first ramp signal and resetting the first control signal responsive to the first ramp signal exceeding the first error signal, the first control signal having an on time when asserted;
asserting a second control signal at a beginning of each period for a second ramp signal and resetting the second control signal responsive to the second ramp signal exceeding the first error signal, the second control signal having an on time when asserted and wherein a total on time equals a sum of the on time for the first control signal and the on time for the second control signal;
responsive to the second error signal, adjusting the on time for the first control signal to produce an adjusted first control signal that is periodically asserted for a first on time and then reset and adjusting the on time for the second control signal to produce an adjusted second control signal that is periodically asserted for a second on time and then reset such that a sum of the first on time and of the second on time equals the total on time; and
selecting from the plurality of four switching configurations for the plurality of switches for the multi-level buck converter responsive to whether the adjusted first control signal and the adjusted second control signal are asserted or reset to regulate the output voltage and the flying capacitor voltage.

11. The method of claim 10 , wherein clamping the first error signal comprising clamping the first error signal responsive to an output voltage from a digital-to-analog converter.

12. The method of claim 10 , wherein the regulation of flying capacitor voltage maintains an average value for the flying capacitor voltage to equal one-half of an input voltage for the multi-level buck converter.

13. The method of claim 10 , wherein clamping the first error signal comprises clamping an error signal voltage.

14. A multi-level buck converter, comprising:
a plurality of switches having four switching states with respect to an inductor and a flying capacitor; and
a first error amplifier configured to produce a first error signal responsive to a difference between an output voltage and a first reference voltage;
a controller configured to select from the four switching states responsive to a comparison of the first error signal to a

Assignees

• Dialog Semiconductor Uk Ltd

Inventors

• Mangudi Aravind
• Mckillop William
• Mercer Mark
• Rahman Muhammad Nabeel
• Dowdy Kevin

Classifications

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M2001/0025

  Electricity · mapped topic

• H02M7/4837 Primary

  Flying capacitor converters · CPC title