Integrated assemblies having transistor body regions coupled to carrier-sink-structures; and methods of forming integrated assemblies

Patent metadata

Field	Value
Publication number	US-11348932-B2
Application number	US-202016810009-A
Country	US
Kind code	B2
Filing date	Mar 5, 2020
Priority date	Mar 6, 2019
Publication date	May 31, 2022
Grant date	May 31, 2022

Abstract

Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

First claim

We claim:

1. An integrated assembly, comprising:
a carrier-sink-structure;
digit lines over the carrier-sink-structure;
transistor body regions over the digit lines;
extensions extending from the carrier-sink-structure to at least a vertical level of the transistor body regions; the extensions being configured to drain excess carriers from the transistor body regions to the carrier-sink-structure;
lower source/drain regions between the transistor body regions and the digit lines; the lower source/drain regions being coupled with the digit lines;
upper source/drain regions over the transistor body regions;
storage elements coupled with the upper source/drain regions;
gates adjacent the transistor body regions; and
the transistor body regions, lower source/drain regions and upper source/drain regions together comprising a plurality of transistors; the transistors and the storage elements together comprising by a plurality of memory cells of a memory array.

2. The integrated assembly of claim 1 wherein the carrier-sink-structure is coupled to a voltage source configured to provide a reference voltage to the carrier-sink-structure.

3. The integrated assembly of claim 2 wherein the carrier-sink-structure is maintained at a constant bias during operation of the transistor body regions.

4. The integrated assembly of claim 1 wherein the transistor body regions are within vertically-extending semiconductor pillars.

5. The integrated assembly of claim 1 wherein the digit lines extend along a first direction; and wherein the lower source/drain regions, the transistor body regions, and the upper source/drain regions are all of a same width as one another along a cross-section orthogonal to the first direction.

6. The integrated assembly of claim 1 wherein the digit lines extend along a first direction; and wherein the lower source/drain regions have a different width relative to the transistor body regions and the upper source/drain regions along a cross-section orthogonal to the first direction.

7. The integrated assembly of claim 1 wherein the storage elements are capacitors.

8. The integrated assembly of claim 7 wherein the memory cells are one-transistor-one-capacitor (1T-1C) memory cells.

9. The integrated assembly of claim 7 wherein the memory cells are two-transistor-one-capacitor (2T-1C) memory cells.

10. The integrated assembly of claim 1 wherein the carrier-sink-structure is p-type.

11. The integrated assembly of claim 1 wherein the carrier-sink-structure is n-type.

12. The integrated assembly of claim 1 wherein the carrier-sink-structure comprises silicon doped to a concentration of at least about 1×10 20 atoms/cm 3 with p-type dopant or n-type dopant.

13. The integrated assembly of claim 12 wherein the extensions comprise silicon doped to a concentration of at least about 1×10 20 atoms/cm 3 with said p-type dopant or n-type dopant.

14. The integrated assembly of claim 1 wherein the extensions directly contact the transistor body regions.

15. The integrated assembly of claim 14 wherein:
the digit lines have a width along a cross-section;
the transistor body regions have ledge regions along the cross-section, with the ledge regions extending outwardly beyond said width and having undersides; and
the extensions directly contact the undersides of the ledge regions.

16. The integrated assembly of claim 1 wherein the extensions are spaced from the transistor body regions by intervening insulative regions.

17. The integrated assembly of claim 16 wherein:
the transistor body regions having vertically-extending sidewalls;
portions of the extensions are laterally adjacent regions of the vertically-extending sidewalls; and
the intervening insulative regions are between the portions of the extensions and the vertically-extending sidewalls.

18. The integrated assembly of claim 16 wherein the intervening insulative regions comprise silicon dioxide.

19. The integrated assembly of claim 16 wherein the intervening insulative regions comprise high-k material.

20. The integrated assembly of claim 16 wherein the intervening insulative regions have thicknesses between the extensions and the transistor body regions within a range of from about 10 Å to about 50 Å.

21. The integrated assembly of claim 1 wherein the memory array is within a tier; the tier being within a vertically-stacked arrangement of tiers and being over at least one other of the tiers within the vertically-stacked arrangement.

Assignees

• Micron Technology Inc

Inventors

• Karda Kamal M
• Liu Haitao
• Ramaswamy Durai Vishak Nirmal
• Gao Yunfei
• Tang Sanh D
• Pandey Deepak Chandra

Classifications

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D30/025 Primary

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• H01L27/11582

  Electricity · mapped topic