Synchronized parallel tile computation for large area lithography simulation

US11340584B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11340584-B2
Application numberUS-202117170389-A
CountryUS
Kind codeB2
Filing dateFeb 8, 2021
Priority dateNov 15, 2017
Publication dateMay 24, 2022
Grant dateMay 24, 2022

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  5. First independent claim

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Abstract

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Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.

First claim

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What is claimed is: 1. A system comprising: a manager machine interacting with a plurality of worker machines including a first work machine and a second worker machine, the manager machine being configured to: receive an IC design layout; partition the IC design layout into a plurality of simulation boxes including a first simulation box and a second simulation box, wherein an overlapping region of the first and second simulation boxes includes a point with a set of coordinates; assign the first and second simulation boxes to the first and second worker machines, respectively, for performing a simulated imaging process including first and second imaging steps; and the first and second worker machines interacting with the manager machine, the first and second worker machines being configured to: in the first imaging step, compute image value A of the point using the first worker machine and image value B of the point using the second worker machine; in the first imaging step, exchange image value A and image value B with each other; and in the second imaging step, compute image value C of the point using the first worker machine and image value D of the point using the second worker machine, wherein the computation of both image value C and image value D is based on a weighted combination of image value A and image value B. 2. The system of claim 1 , wherein the weighted combination of image value A and image value B uses a first weight multiplied by image value A and a second weight multiplied by image value B, and wherein a sum of the first and second weights equals one. 3. The system of claim 1 , wherein image value C of the point computed using the first worker machine and image value D of the point computed using the second worker machine are equal. 4. The system of claim 3 , wherein the first and second worker machines are further configured to send image value C of the point and image value D of the point to the manager machine. 5. The system of claim 4 , wherein the manager machine is further configured to: generate a modified IC design layout based in part on image value C of the point and image value D of the point; and provide the modified IC design layout for fabricating a lithography mask based on the modified IC design layout. 6. The system of claim 1 , wherein the manager machine is a first manager machine, the system further comprising a second manager machine interacting with another plurality of worker machines. 7. The system of claim 1 , wherein the plurality of worker machines further includes a third worker machine, wherein the manager machine assigns a third simulation box to the third worker machine, the third simulation box encompassing the point, and wherein the third worker machine is configured to, in the first imaging step, compute another image value of the point using the third worker machine and exchange the another image value with the image value A and with the image value B. 8. The system of claim 7 , wherein the computation of both image value C and image value D is based on a weighted combination of image value A, image value B, and the another image value. 9. The system of claim 1 , wherein the manager machine is configured to combine the first simulation box with the second simulation box to generate the modified IC design layout. 10. A system comprising: a manager machine configured to: partition an IC design layout into a plurality of simulation boxes, each including an overlapped region, and assign each simulation box of the plurality of simulation boxes to one of a plurality of worker machines; and the plurality of worker machines, each configured to: receive an assignment of a respective simulation box of the plurality of simulation boxes; compute a first image value of a point within the overlapped region of the respective simulation box for a first imaging step; communicate with another worker machine of the plurality of worker machines having a simulation box sharing the overlapped region to provide a first updated image value of the point; compute a second image value of the point for a second imaging step based on the first updated image value of the point. 11. The system of claim 10 , wherein the plurality of worker machines are each further configured to: in a first imaging step, compute an initial image value for an additional point of the respective simulation box outside the overlapped region; and in a second imaging step, compute a second updated image value for the additional point starting from the initial image value. 12. The system of claim 10 , wherein the manager machine is further configured to provide instructions to the plurality of worker machines defining communication partners for each of the plurality of worker machines. 13. The system of claim 10 , wherein the manager machine is a first manager machine, and the system further comprising a second manager machine interacting with another plurality of worker machines. 14. The system of claim 10 , wherein the plurality of worker machines are each configured to provide the first updated image value of the point by computing a weighted average of a first image value of the point calculated by the respective worker machine and a second image value of the point calculated by the another worker machine. 15. The system of claim 10 , wherein the plurality of worker machines are each configured to communicate with the another worker machine to provide a second updated image value of the point based on a weighted average of the second image value and a third image value of the point calculated by the another worker machine for the second imaging step. 16. The system of claim 10 , wherein the plurality of worker machines are each configured to communicate with the another worker machine to provide a second updated image value of the point based on a weighted average of the second image value and a third image value of the point calculated by the another worker machine for the second imaging step. 17. A system comprising: a manager machine configured to: partition an IC design layout into a plurality of simulation boxes, each including an overlapped region; assign each simulation box of the plurality of simulation boxes to one of a plurality of worker machines; and provide instructions to the plurality of worker machines defining communication partners for each of the plurality of worker machines; and the plurality of worker machines, each configured to: receive an assignment of a respective simulation box of the plurality of simulation boxes; compute a first image value of a point within the overlapped region of the respective simulation box for a first imaging step; communicate with another worker machine of the plurality of worker machines having a simulation box sharing the overlapped region to provide a first updated image value of the point; compute a second image value of the point for a second imaging step based on the first updated image value of the point. 18. The system of claim 17 , wherein the plurality of worker machines are each further configured to: in a first imaging step, compute an initial image value for an additional point of the respective simulation box outside the overlapped region; and in a second imaging step, compute a second updated image value for the additional point starting from the initial image value. 19. The system of claim 17 , wherein the manager machine is a first manager machine, and the system further comprising a second manager machine interacti

Assignees

Inventors

Classifications

  • Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

  • Manufacturability analysis or optimisation for manufacturability · CPC title

  • Reflection masks; Preparation thereof · CPC title

  • Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS] · CPC title

  • using simulation · CPC title

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What does patent US11340584B2 cover?
Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a m…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification G03F1/36. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 24 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).