Display controller with multiple common voltages corresponding to multiple refresh rates

Patent metadata

Field	Value
Publication number	US-11335291-B2
Application number	US-201616313401-A
Country	US
Kind code	B2
Filing date	Jul 1, 2016
Priority date	Jul 1, 2016
Publication date	May 17, 2022
Grant date	May 17, 2022

Abstract

A display controller for a display may include a frame rate circuit to change a frame rate of the display from a first frame rate to a second frame rate, and a reference voltage circuit to adjust a reference voltage of the display from a first reference voltage corresponding to the first frame rate to a second reference voltage corresponding to the second frame rate. The display may be a thin film transistor liquid crystal display. The reference voltage may correspond to a common voltage (Vcom) for the display.

First claim

We claim:

1. A liquid crystal display system, comprising:
a liquid crystal display panel;
a source driver circuit coupled to the liquid crystal display panel;
a gate driver circuit coupled to the liquid crystal display panel;
a display connector;
a back light disposed adjacent to the liquid crystal display panel;
a back light driver circuit coupled between the display connector and the back light;
a timing control circuit coupled between the display connector and the source driver circuit, the timing control circuit to set a frame rate of the liquid crystal display panel to one of at least a first frame rate and a second frame rate in accordance with an operation mode; and
a power control circuit coupled between the display connector and the gate driver circuit, the power control circuit to automatically set a reference voltage of the liquid crystal display panel to one of at least a first reference voltage and a second reference voltage in accordance with the operation mode to symmetrically balance a total amount of positive and negative pixel voltage polarities and to reduce flicker when the frame rate is changed, wherein the first reference voltage and the second reference voltage are to be set to a corresponding voltage to reduce or remove flicker in the associated operation mode, and wherein the first reference voltage corresponds to a first pre-determined voltage for the first frame rate and the second reference voltage corresponds to a second pre-determined voltage for the second frame rate.

2. The liquid crystal display system of claim 1 , further comprising: a non-volatile memory storing at least a first value which correlates the first reference voltage with the first frame rate and at least a second value which correlates the second reference voltage with the second frame rate.

3. The liquid crystal display system of claim 2 , wherein the timing control circuit includes a frame rate circuit to set a different frame rate for the liquid crystal display to one of the first frame and the second frame rate in accordance with a change in the operation mode, to retrieve one of the first value and the second value from the non-volatile memory in accordance with the different frame rate, and to provide the retrieved value to the power control circuit.

4. A processing system comprising;
a processor;
a display coupled to the processor; and
a display controller coupled to the display, wherein the display controller includes:
a frame rate circuit to change a frame rate of a display from a first frame rate to a second frame rate, wherein the frame rate circuit is further to change the frame rate of the display from the first frame rate to the second frame rate in accordance with a change in an operation mode, and
a reference voltage circuit to automatically adjust a reference voltage of the display from a first reference voltage corresponding to the first frame rate to a second reference voltage corresponding to the second frame rate to symmetrically balance a total amount of positive and negative pixel voltage polarities and to reduce flicker when the frame rate is changed, wherein the first reference voltage and the second reference voltage are to be set to a corresponding voltage to reduce or remove flicker in the associated operation mode, and wherein the first reference voltage corresponds to a first pre-determined voltage for the first frame rate and the second reference voltage corresponds to a second pre-determined voltage for the second frame rate.

5. The processing system of claim 4 , wherein the display controller further comprises:
a memory storing a first value which correlates the first reference voltage with the first frame rate in a first memory location and a second value which correlates the second reference voltage with the second frame rate in a second memory location.

6. The processing system of claim 4 , wherein the change in the operation mode corresponds to a change in a power mode.

7. The processing system of claim 4 , wherein the frame rate circuit is further to change the frame rate of the display from the first frame rate to a third frame rate, and wherein the reference voltage circuit is further to adjust the reference voltage of the display from the first reference voltage corresponding to the first frame rate to a third reference voltage corresponding to the third frame rate.

8. The processing system of claim 4 , wherein the display comprises a liquid crystal display and wherein the reference voltage corresponds to a common voltage for the liquid crystal display.

9. A display controller comprising:
a frame rate circuit to change a frame rate of a display from a first frame rate to a second frame rate, wherein the frame rate circuit is further to change the frame rate of the display from the first frame rate to the second frame rate in accordance with a change in an operation mode; and
a reference voltage circuit to automatically adjust a reference voltage of the display from a first reference voltage corresponding to the first frame rate to a second reference voltage corresponding to the second frame rate to symmetrically balance a total amount of positive and negative pixel voltage polarities and to reduce flicker when the frame rate is changed, wherein the first reference voltage and the second reference voltage are to be set to a corresponding voltage to reduce or remove flicker in the associated operation mode, and wherein the first reference voltage corresponds to a first pre-determined voltage for the first frame rate and the second reference voltage corresponds to a second pre-determined voltage for the second frame rate.

10. The display controller of claim 9 , further comprising:
a memory storing a first value which correlates the first reference voltage with the first frame rate in a first memory location, and a second value which correlates the second reference voltage with the second frame rate in a second memory location.

11. The display controller of claim 9 , wherein the change in the operation mode corresponds to a change in a power mode.

12. The display controller of claim 9 , wherein the frame rate circuit is further to change the frame rate of the display from the first frame rate to a third frame rate, and wherein the reference voltage circuit is further to adjust the reference voltage of the display from the first reference voltage corresponding to the first frame rate to a third reference voltage corresponding to the third frame rate.

13. A method of controlling a display, comprising:
changing, via a frame rate circuit, a frame rate of the display from a first frame rate to a second frame rate, wherein changing the frame rate includes:
changing an operation mode; and
changing the frame rate of the display from the first frame rate to the second frame rate in accordance with the operation mode; and

automatically adjusting, via a reference voltage circuit, a reference voltage of the display from a first reference voltage corresponding to the first frame rate to a second reference voltage corresponding to the second frame rate to symmetrically balance a total amount of positive and negative pixel voltage polarities and to reduce flicker when the frame rate is changed, wherein the first reference voltage and the second reference voltage are to be set to a corresponding voltage to reduce or remove flicker in the associated operation mode, and wherein the first reference voltage corresponds to a first pre-determined voltage for the first frame rate and the second reference voltage corresponds to a second pre-determined voltage for the second frame rate.

14. The method of claim 1

Assignees

• Intel Corp

Inventors

• Kwak Dongyeung
• Cancel Olmo Ramon C
• Li Jue
• Nugraha Thomas A
• Lang John

Classifications

• G09G3/3614

  Control of polarity reversal in general · CPC title

• G09G2370/08

  Details of image data interface between the display device controller and the data line driver circuit · CPC title

• G09G2320/0252

  Improving the response speed · CPC title

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• G09G2340/0435

  Change or adaptation of the frame rate of the video stream · CPC title