Low power display device with variable refresh rates

Patent metadata

Field	Value
Publication number	US-9318069-B2
Application number	US-201414155297-A
Country	US
Kind code	B2
Filing date	Jan 14, 2014
Priority date	Jan 14, 2013
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

The disclosure describes procedures for dynamically employing a variable refresh rate at an LCD display of a consumer electronic device, such as a laptop computer, a tablet computer, a mobile phone, or a music player device. In some configurations, the consumer electronic device can include a host system portion, having one or more processors and a display system portion, having a timing controller, a buffer circuit, a display driver, and a display panel. The display system can receive image data and image control data from a GPU of the host system, evaluate the received image control data to determine a reduced refresh rate (RRR) for employing at the display panel, and then transition to the RRR, whenever practicable, to conserve power. In some scenarios, the transition to the RRR can be a transition from a LRR of 50 hertz or above to a RRR of 40 hertz or below.

First claim

What is claimed is:

1. A buffer circuit of a display, comprising:
a reference voltage bank selection component storing a plurality of register values; and
a plurality of image buffers, wherein the buffer circuit is configured to:
receive, in response to an identification of an image presentation deficiency, a reference voltage input selection from a timing controller;
compare the reference voltage input selection to the plurality of register values;
select a target reference voltage value based on the comparison;
employ an output bias at least based on the selected target reference voltage;
when the display is operating at a reduced refresh rate, increase a luminosity of the display according to the selected target reference voltage and the reduced refresh rate; and
when the display is operating an increased refresh rate, decrease the luminosity of the display according to the selected target reference voltage and the increased refresh rate.

2. The buffer circuit of claim 1 , wherein the reference voltage input selection is received at a dedicated hardware pin of the buffer circuit.

3. The buffer circuit of claim 1 , wherein the image presentation deficiency is associated with one or more undesirable image artifacts or an altered image luminosity.

4. The buffer circuit of claim 3 , wherein the image presentation deficiency is identified at the buffer circuit or at a graphics processor unit (GPU) that is configured to drive the display.

5. The buffer circuit of claim 3 , wherein the identification of the image processing deficiency corresponds to a detection of a reduced refresh rate employed by the display.

6. The buffer circuit of claim 1 , wherein the buffer circuit is configured to select a slope setting for the selected target reference voltage in order to gradually transition from a current reference voltage output to the selected target reference voltage.

7. A computing device, comprising:
a display device; and
a buffer circuit configured to perform steps that include:
receiving, in response to an identification of an image presentation deficiency, a reference voltage input selection from a timing controller of the computing device, wherein the buffer circuit is configured to operate in one of multiple modes based on a rate of change of the reference voltage input selection;
comparing the reference voltage input selection to a plurality of register values;
selecting a target reference voltage value based on the comparing;
when the display device is operating at a reduced refresh rate, increasing a luminosity of the display device according to the selected target reference voltage and the reduced refresh rate; and
when the display device is operating an increased refresh rate, decreasing the luminosity of the display device according to the selected target reference voltage and the increased refresh rate.

8. The computing device of claim 7 , further comprising:
a graphics processing unit configured to identify the image presentation deficiency and cause a signal to be sent to the buffer circuit.

9. The computing device of claim 7 , further comprising:
wherein the steps further include identifying the image presentation deficiency.

10. The computing device of claim 7 , wherein the buffer circuit is configured to adjust an output bias to conserve an amount of power consumed by the buffer circuit.

11. The computing device of claim 7 , wherein a first mode of the multiple modes corresponds to a greater rate of change of the reference voltage input selection than a second mode of the multiple modes.

12. The computing device of claim 7 , wherein the rate of change of the reference voltage input selection is determined based in part on a counter clock operating at the buffer circuit.

13. The computing device of claim 7 , wherein the buffer circuit is configured to employ an output bias based on the selected target reference voltage.

14. A method for operating a buffer circuit of a display device, the method comprising:
by the buffer circuit:
receiving, in response to an identification of an image presentation deficiency, a reference voltage input selection from a controller of the display device;
comparing the reference voltage input selection to a plurality of register values;
selecting a target reference voltage value based on the comparing;
employing an output bias at least based on the selected target reference voltage;
when the display device is operating at a reduced refresh rate, increasing a luminosity of the display device according to the selected target reference voltage and the reduced refresh rate; and
when the display device is operating an increased refresh rate, decreasing the luminosity of the display device according to the selected target reference voltage and the increased refresh rate.

15. The method of claim 14 , further comprising:
receiving a signal from a graphics processor corresponding to the identification of the image presentation deficiency.

16. The method of claim 14 , further comprising:
identifying, by the buffer circuit, the image presentation deficiency.

17. The method of claim 14 , further comprising:
operating in one of multiple modes based on a rate of change of the reference voltage input selection.

18. The method of claim 17 , wherein a first mode of the multiple modes corresponds to a greater rate of change of the reference voltage input selection than a second mode of the multiple modes.

19. The method of claim 17 , wherein the rate of change of the reference voltage input selection is determined based in part on a counter clock operating at the buffer circuit.

20. The method of claim 14 , further comprising:
adjusting the output bias to conserve an amount of power consumed by the buffer circuit.

Assignees

• Apple Inc

Inventors

• Nambi Prasanna
• Gomez Jason N
• Zheng Fenghua
• Sacchetto Paolo
• Pintz Sandro H
• Kim Taesung
• Tann Christopher P
• Albrecht Marc
• Lum David W

Classifications

• G09G2370/08

  Details of image data interface between the display device controller and the data line driver circuit · CPC title

• G09G3/36

  using liquid crystals · CPC title

• G09G3/3655

  Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors · CPC title

• G09G3/3696 Primary

  Generation of voltages supplied to electrode drivers · CPC title

• G09G3/3618 Primary

  with automatic refresh of the display panel using sense/write circuits · CPC title