Display apparatus and method of driving display panel using the same

US9818364B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9818364-B2
Application numberUS-201514690711-A
CountryUS
Kind codeB2
Filing dateApr 20, 2015
Priority dateAug 27, 2014
Publication dateNov 14, 2017
Grant dateNov 14, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A display apparatus includes a timing controller, a data driver and a display panel. The timing controller receives input image data at a first frequency substantially equal to a frame rate of an input image. The timing controller generates a data signal having the first frequency based on the input image data having the first frequency. The data driver converts the data signal into a data voltage. The display panel displays an image based on the data voltage.

First claim

Opening claim text (preview).

What is claimed is: 1. A display apparatus comprising: a timing controller, a data driver and a display panel; wherein the timing controller receives input image data at a first frequency, the first frequency being substantially equal to a frame rate of an input image, and generates a data signal having the first frequency based on the input image data having the first frequency; the data driver converts the data signal into a data voltage; and the display panel displays an image based on the data voltage, wherein the input image data includes active periods and blank periods which alternate with each other, the timing controller comprises a blank power control part, and the blank power control part controls the data driver to be turned off during the blank period. 2. The display apparatus of claim 1 , further comprising: a decoder, a memory and a graphic processing unit; wherein the decoder decodes the input image; the memory stores the decoded input image in the memory; and the graphic processing unit converts the decoded input image into the input image data having the first frequency and outputs the input image data to the timing controller. 3. The display apparatus of claim 1 , wherein each gap between the active periods are substantially uniform. 4. The display apparatus of claim 3 , wherein a length of the active period is 1/60 second, and a length of the blank period is determined as the each gap of the adjacent active periods. 5. The display apparatus of claim 1 , wherein when the first frequency is 30 Hz (hertz), a length of the active period is substantially equal to a length of the blank period. 6. The display apparatus of claim 1 , wherein when the first frequency is less than 30 Hz (hertz), a length of the active period is less than a length of the blank period. 7. The display apparatus of claim 1 , wherein the timing controller further comprises a register which stores the frame rate of the input image, and the blank power control part which outputs a blank control signal which varies according to the frame rate of the input image. 8. The display apparatus of claim 1 , wherein the data driver comprises: a power control part, a digital to analog converting part, a buffering part, a first switching part, and a second switching part; wherein the power control controls a power according to a blank control signal determined according to the input image; the digital to analog converting part converts the data signal from a digital signal to an analog signal; the buffering part buffers the data voltage; the first switching part turns on during the active periods and applies the data voltage to a data line; and the second switching part turns on during the blank periods and applies a blank voltage to the data line. 9. The display apparatus of claim 8 , wherein the data driver further comprises a power switching part, the power switching part turns off the digital to analog converting part and the buffering part during the blank periods. 10. The display apparatus of claim 8 , wherein the data driver further comprises a blank voltage providing part, the blank voltage providing part provides the blank voltage to the second switching part. 11. The display apparatus of claim 8 , wherein the second switching part comprises: switches in a first row and switches in a second row; wherein the switches in the first row turn on alternately, and apply a first blank voltage to the data line; and the switches in a second row turn on alternately, and apply a second blank voltage to the data line. 12. A method of driving a display panel, the method comprising: receiving input image data at a first frequency substantially equal to a frame rate of an input image; generating a data signal having the first frequency based on the input image data having the first frequency; and displaying an image based on the data signal, wherein the input image data includes active periods and blank periods which alternate with each other, and wherein the timing controller controls a data driver to turn off during the blank periods. 13. The method of claim 12 , further comprising: decoding the input image; storing the decoded input image in a memory; converting the decoded input image into the input image data having the first frequency; and outputting the input image data to a timing controller. 14. The method of claim 12 , wherein each gap between the active periods are substantially uniform. 15. The method of claim 12 , wherein the timing controller further comprises a register which stores the frame rate of the input image. 16. A display apparatus comprising: an application processor which generates input image data having a first frequency based on an input image, wherein the first frequency is substantially equal to a frame rate of the input image; a timing controller which receives the input image data having the first frequency, and generates a data signal having the first frequency based on the input image data having the first frequency; a data driver which converts the data signal into a data voltage; and a display panel displays an image based on the data voltage, wherein a frame of the input image data includes active periods and blank periods, which alternate with each other, a length of each of the active periods in the frame is equal to 1 over a predetermined normal driving frequency of the display panel.

Assignees

Inventors

Classifications

  • using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

  • Power management, e.g. power saving · CPC title

  • Determination of a pixel data signal depending on the signal applied in the previous frame · CPC title

  • Generation of voltages supplied to electrode drivers · CPC title

  • Precharge or discharge of column electrodes before or after applying exact column voltages · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9818364B2 cover?
A display apparatus includes a timing controller, a data driver and a display panel. The timing controller receives input image data at a first frequency substantially equal to a frame rate of an input image. The timing controller generates a data signal having the first frequency based on the input image data having the first frequency. The data driver converts the data signal into a data volt…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3688. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 14 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).