Integrated circuit shield

Patent metadata

Field	Value
Publication number	US-11329010-B2
Application number	US-202016838577-A
Country	US
Kind code	B2
Filing date	Apr 2, 2020
Priority date	Apr 11, 2019
Publication date	May 10, 2022
Grant date	May 10, 2022

Abstract

An anti-tamper layer is applied to a blank wafer. The layered wafer is then diced into shield dies. A shield die is oxide-to-oxide bonded to the top of an active die such that removing the shield die will damage the active die. The shield die may be sized and positioned such that wirebond pads along one or more edges of the active die remain exposed. The exposed wirebond pads may be used to electrically connect, via wirebonds, the active die to a substrate. A second shield die may be attached to the bottom of the active die to help protect against the use of bottom-to-top delayering.

First claim

What is claimed is:

1. An electronic assembly, comprising:
a substrate;
an active integrated circuit die having first and second opposing sides, the first side of the active integrated circuit die including active circuitry, the second side of the active integrated circuit die mounted to the substrate; and,
a first shield die with no active circuits having first and second opposing sides, the first side of the first shield die comprising an anti-tamper layer, the second side of the first shield die bonded to the first side of the active integrated circuit die.

2. The assembly of claim 1 , wherein the active circuitry includes first bond pads for wire bonding connections to second bond pads disposed on the substrate, the second side of the first shield die not overlapping all of the first bond pads.

3. The assembly of claim 1 , wherein the first high-temperature anti-tamper layer is not removable using a process that heats the assembly to less than 350 degrees centigrade.

4. The assembly of claim 1 , wherein the first side of the active integrated circuit die includes an anti-tamper metallization pattern coupled to the active circuitry.

5. The assembly of claim 1 , wherein the second side of the first shield die bonded is to the first side of the active integrated circuit die using oxide to oxide bonding.

6. The assembly of claim 1 , wherein the second side of the first shield die is bonded to the first side of the active integrated circuit die using a process that does not heat the active integrated circuit die to a temperature greater than 170 degrees centigrade.

7. An electronic assembly, comprising:
an active integrated circuit die comprising active circuitry disposed on a first side of the active integrated circuit die, the active integrated circuit die having a second side of the active integrated circuit die opposite the first side of the active integrated circuit die; and,
a first shield die having first and second opposing sides, the first side of the first shield die comprising a first high-temperature anti-tamper layer, the second side of the first shield die bonded to the first side of the active integrated circuit die.

8. The assembly of claim 7 , further comprising:
a substrate, the second side of the active integrated circuit die attached to the substrate.

9. The assembly of claim 8 , wherein the active circuitry includes first bond pads for wire bonding connections to second bond pads disposed on the substrate, the second side of the first shield die not overlapping all of the first bond pads.

10. The assembly of claim 9 , wherein the first high-temperature anti-tamper layer has a melting point that exceeds 350 degrees centigrade.

11. The assembly of claim 7 , wherein the second side of the first shield die is bonded to the first side of the active integrated circuit die using a process that does not heat the active integrated circuit die to a temperature greater than 170 degrees centigrade.

12. An electronic assembly, comprising:
an active integrated circuit die comprising a first majority silicon substrate, the active integrated circuit also die comprising active circuitry disposed on a first side of the active integrated circuit die, the active integrated circuit die having a second side of the active integrated circuit die opposite the first side of the active integrated circuit die; and,
a first shield die comprising a second majority silicon substrate and having first and second opposing sides, the first side of the first shield die comprising a first high-temperature anti-tamper layer, the second side of the first shield die bonded to the first side of the active integrated circuit die.

13. The assembly of claim 12 , wherein the active circuitry includes first bond pads for wire bonding connections and the second side of the first shield die not overlapping all of the first bond pads.

14. The assembly of claim 12 , further comprising:
a substrate, the second side of the active integrated circuit die attached to the substrate.

15. The assembly of claim 14 , wherein the active circuitry includes first bond pads for wire bonding connections to second bond pads disposed on the substrate, the second side of the first shield die not overlapping all of the first bond pads.

Assignees

• Cryptography Res Inc

Inventors

• Best Scott C
• Li Ming
• Bronner Gary B
• Marson Mark Evan

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W72/865

  Die-attach connectors and bond wires · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title