Electronic hardware assembly

Patent metadata

Field	Value
Publication number	US-2016155679-A1
Application number	US-201414899406-A
Country	US
Kind code	A1
Filing date	Jun 27, 2014
Priority date	Jul 2, 2013
Publication date	Jun 2, 2016
Grant date	—

Abstract

An electronic hardware assembly including at least a first and second laminar component, wherein the first laminar components includes a die, the die including a substrate, a functional region and a first protective layer, and the second laminar component includes a second protective layer, wherein the first and second laminar components are arranged in a stack such that the functional region of the first laminar component is arranged within the assembly substantially between first and second protective layers.

First claim

1 . An electronic hardware assembly comprising at least a first and second laminar component, wherein the first laminar components comprises a die, the die comprising a substrate, a functional region and a first protective layer, and the second laminar component comprises a second protective layer, wherein the first and second laminar components are arranged in a stack such that the functional region of the first laminar component is arranged within the assembly substantially between first and second protective layers.

2 . An electronic hardware assembly according to claim 1 in which the protective layer comprises a structure which resists or reacts to attempts to access the functional region of the die.

3 . An electronic hardware assembly according to claim 1 in which the second laminar component comprises a second die, and the second die comprises a substrate, a functional region, and a protective layer, the assembly being arranged such that the functional regions of both the first and second dies lie within the assembly such they are substantially between the two protective layers.

4 . An electronic hardware assembly according to claim 3 in which (i) the dies have the same design or (ii) the dies are configured differently, such that one of the dies has minimal functionality.

5 . An electronic hardware assembly according to claim 3 in which each die is arranged, in use, to have specific functions allocated thereto.

6 . An electronic hardware assembly according to claim 1 in which the second laminar component comprises a second die, and the second die comprises a substrate, a dummy region and a protective layer.

7 . An electronic hardware assembly according to claim 6 wherein the functional layer is arranged between the two protective layers, and the dummy region is arranged such that is outside the protective layers.

8 . An electronic hardware assembly according to claim 6 in which the dummy region comprises (i) a defective functional region or (ii) a functional region which is not used in the electronic hardware assembly.

9 . An electronic hardware assembly according to claim 1 in which there in which the second laminar component comprises a second die, and the second die comprises a substrate and a protective layer.

10 . An electronic hardware assembly according to claim 1 in which the second laminar component comprises a lid of a hardware package.

11 . An electronic hardware assembly according to claim 10 in which the protective layer comprises one or more printed circuit boards.

12 . An electronic hardware assembly according to claim 10 in which there is an electrical connection between the protective layer in the lid and the functional region of the die.

13 . An electronic hardware assembly according to claim 1 in which the laminar components are electrically interconnected.

14 . An electronic hardware assembly according to claim 13 in which the laminar components are electrically interconnected through Vertical Interconnect Accesses (vias).

15 . An electronic hardware assembly according to claim 14 in which the vias are inter-connected with the protective layer.

16 . An electronic hardware assembly according to claim 1 which further comprises at least one monitor, arranged between the protective layers and provided to monitor the protective layers.

17 . An electronic hardware assembly according to claim 16 in which a single monitor is provided to monitor the protective layers of the first and the second laminar components.

18 . An electronic hardware assembly according to claim 16 in which the monitor is provided within the functional region of a laminar component.

19 . An electronics hardware package which comprises an electronics hardware assembly according to claim 1 , wherein the second laminar component comprises a lid of the package.

20 . An electronics hardware package according to claim 19 , wherein the lid is interconnected with the die using through-package vias.

21 - 22 . (canceled)

Assignees

• Qinetiq Ltd

Inventors

• Davies Nigel Clement
• Lees David John

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title