Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11328969-B2
Application number	US-201715815243-A
Country	US
Kind code	B2
Filing date	Nov 16, 2017
Priority date	Nov 16, 2017
Publication date	May 10, 2022
Grant date	May 10, 2022

Abstract

A semiconductor device includes a first semiconductor die, a first encapsulant surrounding the first semiconductor die, and a first redistribution structure formed on the first semiconductor die and the first encapsulant. The semiconductor device further includes a second semiconductor die, a second encapsulant surrounding the second semiconductor die, and a second redistribution structure formed on the second semiconductor die and the second encapsulant. The semiconductor device also include a conductive via electrically connecting the first redistribution structure to the second redistribution structure.

First claim

What is claimed is:

1. A semiconductor device comprising:
an upper semiconductor die including a bond pad on a top side of the upper semiconductor die;
a lower semiconductor die including a bond pad on a bottom side of the lower semiconductor die, wherein a top side of the lower semiconductor die is below a bottom side of the upper semiconductor die;
an encapsulant contacting and surrounding the upper semiconductor die and the lower semiconductor die, a top side of the encapsulant exposing the bond pad of the upper semiconductor die, and a bottom side of the encapsulant exposing the bond pad of the lower semiconductor die, wherein the encapsulant is interposed between the bottom side the upper semiconductor die and the top side of the lower semiconductor die;
an upper redistribution structure on the upper semiconductor die and the top side of the encapsulant, the upper redistribution structure connected to the bond pad of the upper semiconductor die;
a lower redistribution structure below the lower semiconductor die and the encapsulant and connected to the bond pad of the lower semiconductor die; and
a conductive via through the encapsulant, wherein an upper end of the conductive via is coupled to the upper redistribution structure and a lower end of the conductive via is coupled to the lower redistribution structure.

2. The semiconductor device of claim 1 , wherein the upper semiconductor die includes one of a fingerprint sensor, an optical sensor, a pressure sensor, an accelerometer, a gyro sensor, or a microelectromechanical systems (MEMS) device.

3. The semiconductor device of claim 1 , further comprising:
an external interconnection structure coupled to the lower redistribution structure,
wherein the external interconnection structure includes one of a metal pillar, a solder bump, a solder ball, a land, or a flexible circuit board.

4. The semiconductor device of claim 1 , wherein:
the lower redistribution structure includes:
a first metal layer on the bottom side of the lower semiconductor die and the bottom side of the encapsulant, the first metal layer connecting the bond pad of the lower semiconductor die to the conductive via; and
a first dielectric layer on the first metal layer; and

the upper redistribution structure includes:
a second metal layer on the top side of the upper semiconductor die and the top side of the encapsulant, the second metal layer connecting the bond pad of the upper semiconductor die to the conductive via; and
a second dielectric layer on the second metal layer.

5. The semiconductor device of claim 4 , wherein the conductive via connects the first metal layer of the lower redistribution structure to the second metal layer of the upper redistribution structure.

6. The semiconductor device of claim 4 , further comprising an external interconnection structure coupled to the first metal layer of the lower redistribution structure.

7. The semiconductor device of claim 1 , wherein:
the upper semiconductor die includes sensing circuitry configured to sense phenomena through a sensing region of the top side of the upper semiconductor die;
the upper redistribution structure comprises one or more metal layers;
metal from the one or more metal layers does not extend over the sensing region of the top side of the upper semiconductor die; and
the sensing circuitry is configured to sense, through the sensing region of the upper semiconductor die and the upper redistribution structure, phenomena of an environment external to the semiconductor device without obstruction from the metal of the one or more metal layers.

8. The semiconductor device of claim 1 , wherein the encapsulant comprises an encapsulant upper portion that surrounds the upper semiconductor die and an encapsulant lower portion that surrounds the upper semiconductor die.

9. The semiconductor device of claim 8 , wherein the encapsulant upper portion and the encapsulant lower portion are integrated and form a single integrated body of the encapsulant.

10. The semiconductor device of claim 8 , wherein the encapsulant upper portion and the encapsulant lower portion are integrated and lack a discernable boundary between the encapsulant upper portion and the encapsulant lower portion.

11. The semiconductor device of claim 1 , further comprising an external interconnection structure coupled to the lower redistribution structure.

12. The semiconductor device of claim 1 , further comprising an insulating layer interposed between the conductive via and the encapsulant.

Assignees

• Amkor Tech Singapore Holding Pte Ltd

Inventors

• Na Do Hyun
• Park Sung Soon
• Kim Dae Gon

Classifications

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/244

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/30

  Die-attach connectors · CPC title