Fan-out stacked system in package (sip) and the methods of making the same

US2017194290A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2017194290-A1
Application numberUS-201715464011-A
CountryUS
Kind codeA1
Filing dateMar 20, 2017
Priority dateApr 17, 2014
Publication dateJul 6, 2017
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method comprising: forming one or more first redistribution layers (RDLs) over a carrier; forming a plurality of first conductive columns over the carrier; attaching a first device die to the one or more first RDLs, the first device die being interposed between adjacent ones of the a plurality of first conductive columns; dispensing a first molding compound over the first device die and the one or more first RDLs, the first molding compound extending along a sidewall of the first device die and sidewalls of the plurality of first conductive columns; forming one or more second RDLs over the first device die and the first molding compound, the one or more second RDLs being electrically coupled to the first device die; forming a plurality of second conductive columns over the one or more second RDLs; attaching a second device die to the one or more second RDLs, the second device die being interposed between adjacent ones of the plurality of second conductive columns, the one or more second RDLs being interposed between the first device die and the second device die; dispensing a second molding compound over the second device die and the one or more second RDLs, the second molding compound extending along a sidewall of the second device die and sidewalls of the plurality of second conductive columns; forming one or more third RDLs over the second device die and the second molding compound; forming one or more external connectors over the one or more third RDLs, the one or more external connectors being electrically coupled to the one or more third RDLs; debonding the carrier from the one or more first RDLs; and after debonding the carrier from the one or more first RDLs, attaching a third device die to the one or more first RDLs, the one or more first RDLs being interposed between the first device die and the third device die. 2 . The method of claim 1 , further comprising attaching a fourth device die to the one or more first RDLs adjacent the first device die, wherein a gap between the fourth device die and the first device die is filled with the first molding compound. 3 . The method of claim 1 , further comprising attaching a fifth device die to the one or more first RDLs adjacent the third device die, wherein the one or more first RDLs is interposed between the fifth device die and the first device die. 4 . The method of claim 1 , further comprising, before attaching a third device die to the one or more first RDLs, exposing conductive features of the one or more first RDLs. 5 . The method of claim 1 , wherein the one or more third RDLs are electrically coupled to the second device die. 6 . The method of claim 1 , wherein the one or more first RDLs are electrically coupled to the third device die. 7 . The method of claim 1 , wherein the one or more second RDLs electrically couple the plurality of first conductive columns to the plurality of second conductive columns. 8 . A method comprising: attaching a first device die to a carrier; dispensing a first molding compound over the first device die and the carrier; exposing first connectors on the first device die, a topmost surface of the first molding compound being level with topmost surfaces of the first connectors; forming one or more first redistribution layers (RDLs) over the first device die and the first molding compound, the one or more first RDLs being electrically coupled to the first device die; forming a plurality of conductive columns over the one or more first RDLs; attaching a first device die stack to the one or more first RDLs using second connectors, the first device die stack being interposed between adjacent ones of the plurality of conductive columns, the first device die stack comprising a second device die bonded to a third device die, a backside of the second device die facing a backside of the third device die; dispensing a second molding compound over the first device die stack and the one or more first RDLs, the second molding compound extending along a sidewall of the second device die, a sidewall of the third device die, and sidewalls of the plurality of conductive columns; exposing third connectors on the third device die, a topmost surface of the second molding compound being level with topmost surfaces of the third connectors and topmost surface of the plurality of conductive columns; forming one or more second RDLs over the first device die stack and the second molding compound; and forming one or more external connectors over the one or more second RDLs, the one or more external connectors being electrically coupled to the one or more second RDLs. 9 . The method of claim 8 , further comprising, before dispensing the second molding compound, attaching a second device die stack to the one or more first RDLs using third connectors, the second device die stack comprising a fourth device die bonded to a fifth device die, a backside of the fourth device die facing a backside of the fifth device die, at least one of the plurality of conductive columns being interposed between the second device die stack and the first device die stack. 10 . The method of claim 9 , further comprising, before forming the one or more second RDLs, exposing third connectors on the fifth device die, the topmost surface of the second molding compound being level with topmost surfaces of the third connectors and the topmost surface of the plurality of conductive columns. 11 . The method of claim 10 , wherein the fourth device die is interposed between the fifth device die and the one or more first RDLs. 12 . The method of claim 8 , wherein the second device die is interposed between the third device die and the one or more first RDLs. 13 . The method of claim 8 , further comprising debonding the carrier from the first device die. 14 . The method of claim 8 , wherein the plurality of conductive columns electrically couples the one or more first RDLs to the one or more second RDLs. 15 . A method comprising: forming one or more first redistribution layers (RDLs) over a first carrier; forming a plurality of first conductive columns over the one or more first RDLs; attaching a first device die to the one or more first RDLs, the first device die being interposed between adjacent ones of the plurality of first conductive columns; dispensing a first molding compound over the first device die and the one or more first RDLs; forming one or more second RDLs over the first device die and the first molding compound, the one or more second RDLs being electrically coupled to the first device die; forming one or more first external connectors over the one or more first RDLs, the one or more first external connectors being electrically coupled to the one or more first RDLs; forming one or more third RDLs over a second carrier; forming a plurality of second conductive columns over the one or more third RDLs; attaching a device die stack to the one or more third RDLs, the device die stack being interposed between adjacent ones of the plurality of second conductive columns, the device die stack comprising a second device die bonded to a third device die, a backside of the second device die facing a backside of the third device die; dispensing a second molding compound over the device die stack and the one or more third RDLs, the second molding compound extending along a sidewall of the second device die, a sidewall of the third device die, and sidewalls of the plurality of second conductive columns; forming one or more fourth RDLs over the device die stack and the second molding compound; formin

Assignees

Inventors

Classifications

  • used as a support during the manufacture of self-supporting substrates · CPC title

  • used as a support during manufacture of interconnect decals or build up layers · CPC title

  • using temporarily an auxiliary support · CPC title

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

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What does patent US2017194290A1 cover?
An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device di…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jul 06 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).