Tiered ECC single-chip and double-chip Chipkill scheme

Patent metadata

Field	Value
Publication number	US-9772900-B2
Application number	US-201514606334-A
Country	US
Kind code	B2
Filing date	Jan 27, 2015
Priority date	Jul 10, 2014
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

Exemplary embodiments provide a tiered error correction code (ECC) Chipkill system, comprising: a device ECC incorporated into at least a portion of a plurality of memory devices that corrects n-bit memory device-level failures in the respective memory device, and transmits a memory device failure signal when any memory device-level failure is greater than n-bits and beyond correction capability of the device ECC device; and a system-level ECC device external to the plurality of memory devices is responsive to receiving the memory device failure signal to correct the memory device failure based on a system ECC parity.

First claim

We claim:

1. A tiered error correction code (ECC) system, comprising:
a memory device-level comprising a plurality of memory devices within a memory module, and a device ECC apparatus associated with the plurality of memory devices, wherein the device ECC apparatus comprises a device ECC engine in each of the plurality of memory devices, and a row parity chip that comprises one of the plurality of memory devices and contains parity information for the plurality of memory devices;
wherein the device ECC engine corrects n-bit memory device-level failures in the respective memory device using the parity information in the row parity chip, and transmits a memory device failure signal when any memory device-level failure is greater than n-bits and beyond correction capability of the device ECC device; and
a system-level comprising a system-level ECC engine and a system ECC device parity, wherein the system-level ECC device is external to the plurality of memory devices and is responsive to receiving the memory device failure signal to correct the memory device failure based on the system ECC parity.

2. The system of claim 1 , wherein the tiered ECC system corrects a single memory device failure and detects any number of device failures and their locations within a memory module.

3. The system of claim 1 , wherein the memory device failure signal transmitted by the memory devices comprises an ECC failure signal, the ECC failure signal transmitted using an additional data-bus burst or an extra pin, such that receipt of a particular memory device failure signal automatically informs the system ECC engine of an identity of the transmitting memory device and a location of the error.

4. The system of claim 1 , wherein the row parity chip provides the memory devices with n-bit correction capability and is used to correct single chip failures, where n equals one or two.

5. A method of providing a tiered ECC system, comprising:
at a memory device-level comprising a plurality of memory devices within a memory module, associating a device ECC apparatus with the plurality of memory devices wherein the device ECC apparatus comprises a device ECC engine in each of the plurality of memory devices, and a row parity chip that comprises one of the plurality of memory devices and contains parity information for the plurality of memory devices;
using the device ECC engine to correct n-bit memory device-level failures in the respective memory device using the parity information in the row parity chip, and to transmit a memory device failure signal when any memory device-level failure is greater than n-bits and beyond correction capability of the device ECC device; and
at a system-level comprising a system-level ECC engine and a system ECC device parity, using a system-level ECC device external to the plurality of memory devices that is responsive to receiving the memory device failure signal to correct the memory device failure based on the system ECC parity.

6. The method of claim 5 , further comprising: using the tiered ECC system to correct a single memory device failure and to detect any number of device failures and their locations within a memory module.

7. The method of claim 5 , wherein the memory device failure signal transmitted by each of the at least a portion of the memory devices comprises an ECC failure signal, the ECC failure signal transmitted using an additional data-bus burst or an extra pin, such that receipt of a particular memory device failure signal automatically informs the system ECC engine of an identity of the transmitting memory device and a location of the error.

8. The method of claim 5 , wherein the row parity chip provides the memory devices with n bit correction capability and is used to correct single chip failures, where n equals one or two.

9. A tiered error correction code (ECC) system, comprising:
a memory device-level comprising a plurality of memory devices within a memory module;
a device ECC engine in each of the plurality of memory devices;
a row parity chip that comprises one of the plurality of memory devices and contains parity information for the plurality of memory devices;
wherein the device ECC engine corrects n-bit memory device-level failures in the respective memory device using the parity information in the row parity chip, and transmits a memory device failure signal when any memory device-level failure is greater than n-bits and beyond correction capability of the device ECC device;
wherein the memory device failure signal is integrated into a data-bus cyclic redundancy check (CRC) data, and wherein the memory device failure signal comprises 1 bit, the CRC data comprises 7 bits, and a burst length of the data-bus is increased to 10; and
a system-level comprising a system-level ECC engine and a system ECC device parity, wherein the system-level ECC device is external to the plurality of memory devices and is responsive to receiving the memory device failure signal to correct the memory device failure based on the system ECC parity.

10. A tiered error correction code (ECC) system, comprising:
a memory device-level comprising a plurality of memory devices within a memory module;
a device ECC engine in each of the plurality of memory devices;
a row parity chip that comprises one of the plurality of memory devices and contains parity information for the plurality of memory devices;
wherein the device ECC engine corrects n-bit memory device-level failures in the respective memory device using the parity information in the row parity chip, and transmits a memory device failure signal when any memory device-level failure is greater than n-bits and beyond correction capability of the device ECC device;
a diagonal parity chip to extend single-chip correction of a single-chip Chipkill system to a tiered ECC double-chip Chipkill system that performs double-chip correction plus an ability to detect any number of failures in the memory devices comprising the memory module; and
a system-level comprising a system-level ECC engine and a system ECC device parity, wherein the system-level ECC device is external to the plurality of memory devices and is responsive to receiving the memory device failure signal to correct the memory device failure based on the system ECC parity.

11. The system of claim 10 , wherein when there are two memory device failures and two corresponding memory device failure signals, and wherein the system ECC engine uses the diagonal parity chip and the row parity chip alternatively to recover data from the failed memory devices.

12. The system of claim 11 , wherein responsive to the system ECC engine receiving more than two memory device failure signals, the system ECC engine determines which ones of the memory devices failed and the number of memory devices that failed based on the memory device failure signals and sends an uncorrectable error signal to a memory controller.

13. A method of providing a tiered ECC system, comprising:
at a memory device-level comprising a plurality of memory devices within a memory module, associating a device ECC apparatus with the plurality of memory devices, wherein the device ECC apparatus comprises a device ECC engine in each of the plurality of memory devices, and a row parity chip that comprises one of the plurality of memory devices and contains parity information for the plurality of memory devices;
using the device ECC engine to correct n-bit memory device-level failures in the respective memory device using the parity information in the row parity chip, and to transmit a memory device failure signal when any memory device-level failure is greater than n-bits and beyond co

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hu Chaohong
• Kang Uksong
• Zheng Hongzhong

Classifications

• G06F11/108 Primary

  Parity data distribution in semiconductor storages, e.g. in SSD · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F2211/1057

  Parity-multiple bits-RAID6, i.e. RAID 6 implementations · CPC title

• G06F11/1044 Primary

  with specific ECC/EDC distribution · CPC title

• G06F11/1024

  Identification of the type of error · CPC title