Data sampling with loop-unrolled decision feedback equalization

Patent metadata

Field	Value
Publication number	US-11323117-B1
Application number	US-202117305571-A
Country	US
Kind code	B1
Filing date	Jul 9, 2021
Priority date	Jul 9, 2021
Publication date	May 3, 2022
Grant date	May 3, 2022

Abstract

Various embodiments provide for data sampling with loop-unrolled decision feedback equalization. In particular, some embodiments provide for an unrolled first-tap Decision Feedback Equalizer (DFE) loop that comprises parallel data samplers that each include a tri-state output.

First claim

What is claimed is:

1. A circuit comprising:
a first data sampler comprising a first sampler input, a first selection input, and a first tri-state output, the first data sampler being configured to receive an input data signal by the first sampler input, to generate a first sample signal based on a first-tap coefficient with a first polarity, the input data signal and a clock signal, and to output the first sample signal by the first tri-state output, the first tri-state output being controlled based on a first selection signal received by the first selection input, the first selection signal being based on a feedback signal;
a second data sampler comprising a second sampler input, a second selection input, and a second tri-state output, the second data sampler being configured to receive the input data signal by the second sampler input, to generate a second sample signal based on the first-tap coefficient with a second polarity, the input data signal, and the clock signal, and to output the second sample signal by the second tri-state output, the second tri-state output being controlled based on a second selection signal received by the second selection input, the second selection signal being based on an inverted feedback signal; and
a regenerative latch portion coupled to the first tri-state output and the second tri-state output, the regenerative latch portion being configured to receive a sampler output signal from at least one of the first tri-state output or the second tri-state output, to latch the sampler output signal based on the clock signal, to regenerate the latched sampler output signal, and to provide the regenerated latched sampler output signal.

2. The circuit of claim 1 , wherein the input data signal comprises a differential pair of data signals.

3. The circuit of claim 1 , wherein the first-tap coefficient with the first polarity and the first-tap coefficient with the second polarity are associated with a first tap of a decision feedback equalizer implemented by the circuit.

4. The circuit of claim 1 , wherein the regenerative latch portion comprises a cross-coupled inverter.

5. The circuit of claim 4 , wherein the regenerative latch portion comprises a reset input to receive a reset signal, the reset signal being generated based on the clock signal.

6. The circuit of claim 5 , wherein the reset signal is asymmetrical such that regeneration time of the regenerative latch portion is maximized.

7. The circuit of claim 1 , wherein each of the first and the second data samplers has a signal output operating in current mode.

8. The circuit of claim 1 , wherein the first tri-state output is disabled in response to the first selection signal indicating selection of a disabled state.

9. The circuit of claim 1 , wherein the first tri-state output is enabled in response to the first selection signal indicating selection of an enabled state.

10. The circuit of claim 1 , wherein the first data sampler comprises a first set of dummy devices that couples between the first tri-state output and the regenerative latch portion, and wherein the second data sampler comprises a second set of dummy devices that couples between the second tri-state output and the regenerative latch portion.

11. The circuit of claim 1 , wherein the clock signal is a first clock signal, wherein the feedback signal is a first feedback signal, wherein the regenerative latch portion is a first regenerative latch portion, wherein the sampler output signal is a first sampler output signal, wherein the latched sampler output signal is a first latched sampler output signal, wherein the regenerated latched sampler output signal is a first regenerated latched sampler output signal, wherein the inverted feedback signal is an inverted first feedback signal, and wherein the circuit comprises:
a third data sampler comprising a third sampler input, a third selection input, and a third tri-state output, the third data sampler being configured to receive the input data signal by the third sampler input, to generate a third sample signal based on the first-tap coefficient with the first polarity, the input data signal, and a clock signal, and to output the third sample signal by the third tri-state output, the third tri-state output being controlled based on a third selection signal received by the third selection input, and the third selection signal being based on a second feedback signal;
a fourth data sampler comprising a fourth sampler input, a fourth selection input, and a fourth tri-state output, the fourth data sampler being configured to receive the input data signal by the fourth sampler input, to generate a fourth sample signal based on the first-tap coefficient with the second polarity, the input data signal, and the clock signal, and to output the fourth sample signal by the fourth tri-state output, the fourth tri-state output being controlled based on a fourth selection signal received by the fourth selection input, the fourth selection signal being based on an inverted second feedback signal; and
a second regenerative latch portion coupled to the third tri-state output and the fourth tri-state output, the second latch portion being configured to receive a second sampler output signal from at least one of the third tri-state output or the fourth tri-state output, to latch the second sampler output signal based on the second clock signal, to regenerate the second latched sampler output signal, and to provide the second regenerated latched sampler output signal, the first feedback signal comprising the second regenerated sampler output signal, and the second feedback signal comprising the first regenerated sampler output signal.

12. The circuit of claim 11 , comprising:
a multiplexer comprising a multiplexer selection input to receive a multiplexer selection signal, the multiplexer selection signal being generated based on the first clock signal, and the multiplexer being configured to receive the first regenerated latched sampler output signal from the first regenerative latch portion, to receive the second regenerated latched sampler output signal from the second regenerative latch portion, and to selectively output, based on the multiplexer selection signal, the first regenerated latched sampler output signal or the second regenerated latched sampler output signal as a multiplexer output signal;
a second tap scaling component to receive the multiplexer output signal and to generate a second-tap feedback signal based on a second-tap coefficient and the multiplexer output signal; and
an analog summer to receive a received data signal, to receive the second-tap feedback signal, and to generate the input data signal by applying the second-tap feedback signal to the received data signal.

13. The circuit of claim 1 , wherein the regenerative latch portion comprises an additional latch configured to preserve the regenerated latched sampler output signal when the regenerative latch portion enters a reset phase.

14. A non-transitory computer-readable medium comprising instructions that, when executed by one or more processors of a computing device, cause the computing device to generate a circuit design by performing operations comprising:
configuring, in a circuit design, a first data sampler that comprises a first sampler input, a first selection input, and a first tri-state output, the first data sampler being configured to receive an input data signal by the first sampler input, to generate a first sample signal based on a first-tap coefficient with a first polarity, the input data signal and a clock signal, and to output the first sample signal by the first tri-state outp

Assignees

• Cadence Design Systems Inc
• Cadenee Design Systems Inc

Inventors

• Tanguay Louis-Francois
• Delage Jean-Francois
• Fortin Guillaume

Classifications

• H03K5/086 Primary

  generated by feedback · CPC title

• H03K19/09425 Primary

  Multistate logic (H03K19/096 takes precedence) · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K19/096

  Synchronous circuits, i.e. using clock signals {(H03K19/01728, H03K19/01855 take precedence)} · CPC title

• H03K19/17744

  for input/output signals · CPC title