Compensating offsets in buffers and related systems, methods, and devices

Patent metadata

Field	Value
Publication number	US-11322194-B2
Application number	US-202117147976-A
Country	US
Kind code	B2
Filing date	Jan 13, 2021
Priority date	Oct 10, 2019
Publication date	May 3, 2022
Grant date	May 3, 2022

Abstract

Compensating for offsets in buffers and related systems, methods, and devices are disclosed. An apparatus includes buffers, control circuitry, and fuses. Each of the buffers includes an output and an offset adjustment input. Each of the buffers is controllable to adjust a direct current offset of an output voltage potential responsive to an offset adjustment code provided to the offset adjustment input. The control circuitry includes sets of offset latches. The offset adjustment input of each of the buffers is operably coupled to a different one of the sets of offset latches. Each set of offset latches is configured to provide the offset adjustment code to the offset adjustment input of a corresponding buffer. The fuses are configured to provide the offset adjustment code to each of a subset of the sets of offset latches.

First claim

What is claimed is:

1. An apparatus, comprising:
buffers, each of the buffers including an output and an offset adjustment input, each of the buffers controllable to adjust a direct current offset of an output voltage potential at the output responsive to an offset adjustment code provided to the offset adjustment input; and
control circuitry configured to provide the offset adjustment code to the offset adjustment input of each of the buffers.

2. The apparatus of claim 1 , further comprising fuses operably coupled to the control circuitry, the fuses configured to store offset adjustment codes for at least a subset of the buffers and provide the offset adjustment codes to the control circuitry.

3. The apparatus of claim 2 , wherein the offset adjustment codes for the at least the subset of the buffers include offset adjustment codes for each of the buffers.

4. The apparatus of claim 2 , wherein:
the offset adjustment codes for the at least the subset of the buffers include non-zero offset adjustment codes for only a first subset of the buffers, the non-zero offset adjustment codes indicating non-zero offset adjustment of the direct current offset of the output voltage potential at each of the first subset of the buffers; and
the control circuitry is configured to provide zero offset adjustment codes to offset adjustment inputs of a second subset of the buffers, the zero offset adjustment codes indicating zero offset adjustment of the direct current offset of the output voltage potential at each of the second subset of the buffers.

5. The apparatus of claim 2 , wherein a number of the fuses is less than a product between a number of the buffers and a number of bits in the offset adjustment codes.

6. The apparatus of claim 2 , wherein the fuses are further configured to store identification codes associated with the offset adjustment codes stored by the fuses, the identification codes configured to indicate which of the buffers the offset adjustment codes should be provided to.

7. The apparatus of claim 2 , wherein the fuses are further configured to store skip codes associated with the offset adjustment codes, the skip codes indicating numbers of the buffers to skip in an ordered sequence of the buffers to identify the buffers the offset adjustment codes should be provided to.

8. The apparatus of claim 1 , wherein offset adjustment codes are multiple bit offset adjustment codes to accommodate more than two offset values of the offset adjustment code.

9. A method of adjusting direct current offsets of output voltage potentials at outputs of buffers, the method comprising:
providing offset adjustment codes to offset adjustment inputs of the buffers, the offset adjustment codes indicating amounts of offset adjustment to be applied to the output voltage potentials at the outputs of the buffers; and
adjusting the direct current offsets of the output voltage potentials by the amounts of offset adjustment indicated by the offset adjustment codes.

10. The method of claim 9 , further comprising storing at least a subset of the offset adjustment codes corresponding to at least a subset of the buffers in a data storage device.

11. The method of claim 10 , wherein storing the at least the subset of the offset adjustment codes corresponding to at least a subset of the buffers in the data storage device includes storing the at least the subset of the offset adjustment codes in fuses.

12. The method of claim 10 , wherein storing the at least the subset of the offset adjustment codes comprises storing a number of the offset adjustment codes that is equal to a number of the buffers.

13. The method of claim 10 , wherein storing the at least the subset of the offset adjustment codes comprises storing a number of the offset adjustment codes that is less than a number of the buffers.

14. The method of claim 13 , wherein providing the offset adjustment codes to the offset adjustment inputs of the buffers includes:
providing, to the subset of the buffers, the subset of the offset adjustment codes to the subset of the buffers; and
providing, to others of the buffers outside of the subset of the buffers, zero offset adjustment codes indicating zero offset adjustment.

15. The method of claim 10 , further comprising storing identification codes identifying those of the buffers the stored at least a subset of the offset adjustment codes should be provided to.

16. The method of claim 10 , further comprising storing skip codes indicating numbers of the buffers to skip in an ordered sequence of the buffers to identify the buffers the offset adjustment codes should be provided to.

17. An apparatus, comprising:
input terminals;
buffers operably coupled to the input terminals, the buffers configured to provide output voltage potentials responsive to input signals received at the input terminals, the buffers configured to adjust direct current offsets of the output voltage potentials responsive to offset adjustment codes provided to the buffers; and
control circuitry operably coupled to the buffers, the control circuitry configured to provide the offset adjustment codes to the buffers.

18. The apparatus of claim 17 , wherein the buffers are input buffers of a memory device for buffering the input signals including write data to be written to the memory device.

19. The apparatus of claim 17 , further comprising a data storage device configured to store a number of the offset adjustment codes that is less than a number of the buffers for a subset of the buffers, wherein the control circuitry is configured to provide a zero offset adjustment code indicating zero offset adjustment to others of the buffers outside of the subset of the buffers.

20. The apparatus of claim 19 , wherein the data storage device comprises fuses for storing the offset adjustment codes.

Assignees

• Micron Technology Inc

Inventors

• Someya Minoru
• Suzuki Yukihide
• Okuma Sadayuki

Classifications

• G11C2207/2254

  Calibration · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C11/4093 Primary

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C5/147 Primary

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C7/1093

  Input synchronization · CPC title