Apparatus of offset voltage adjustment in input buffer

Patent metadata

Field	Value
Publication number	US-9792964-B1
Application number	US-201615270996-A
Country	US
Kind code	B1
Filing date	Sep 20, 2016
Priority date	Sep 20, 2016
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes an input pad, an input buffer including a first input node and a second input node, a switch that couples the first input node and the second input node in an active state and further decouples the first input node and the second input node in an inactive state, a control circuit that provides a signal causing the switch to be in the active state or an inactive state. The first input node of the input buffer is coupled to the input pad by a conductive wiring.

First claim

What is claimed is:

1. An apparatus comprising:
an input pad;
a first phase;
a first input buffer including a first input node and a second input node;
a conductive wiring configured to permanently couple between the input pad and the first input node of the first input buffer; and
a first switch configured to couple the input pad to the second input node of the first input buffer; and
wherein the first input buffer receives an active signal from an external terminal responsive to an enabling signal in the first phase.

2. The apparatus of claim 1 , further comprising:
a reference voltage generator coupled to the second input node of the first input buffer and configured to generate a reference voltage.

3. The apparatus of claim 2 , wherein the first input buffer is configured to provide a signal responsive to a relative voltage that is a first voltage at the first input node relative to a second voltage at the second input node, and
wherein the first input buffer is configured to receive a test signal and further configured to adjust the relative voltage responsive to the test signal.

4. The apparatus of claim 2 , further comprising:
a second input buffer including a third input node and a fourth input node; and
a second switch configured to couple the input pad to the third input node of the second input buffer.

5. The apparatus of claim 4 , wherein the input pad is configured to provide at least a part of a command, and
wherein the second switch is configured to couple the input pad and the third input node of the second input buffer responsive to at least part of a command provided to the input pad.

6. The apparatus of claim 1 , further comprising an enable input pad,
wherein the first switch is configured to couple the input pad and the second input node responsive to an enable signal provided to the enable input pad.

7. The apparatus of claim 6 , further comprising a reference voltage generator coupled to the second input node of the first input buffer and configured to generate a reference voltage,
wherein one of the reference voltage generator and the input pad is configured to provide the reference voltage to the first input node and the second input node responsive to the enable signal, and
wherein the other of the reference voltage generator and the input pad is at a floating state responsive to the enable signal.

8. An apparatus comprising:
an input pad;
a first input buffer including a first input node and a second input node, the first input node being permanently coupled to the input pad; and
a first switch coupled between the first and second input nodes of the first input buffer, wherein the apparatus is configured to perform operations in a normal mode and a test mode, the test mode comprising a first phase and a second phase,
wherein the first switch is open in the normal mode; and
wherein the first switch is open in the first phase of the test mode and the first switch is closed responsive, at least in part, to a change of the test mode from the first phase to the second phase; and
wherein the first input buffer adjusts an offset voltage in the second phase responsive to a test signal.

9. The apparatus of claim 8 , further comprising:
a reference voltage generator configured to provide a reference voltage to the second input node of the first input buffer in the normal mode and the first phase of the test mode.

10. The apparatus of claim 9 , wherein the reference voltage generator is further configured to stop providing the reference voltage in the second phase of the test mode.

11. The apparatus of claim 10 , wherein the input pad is configured to receive a reference voltage in the second phase of the test mode.

12. The apparatus of claim 8 , further comprising:
a reference voltage generator configured to provide a reference voltage to the second input node of the first input buffer in the normal mode, the first phase of the test mode and the second phase of the test mode.

13. The apparatus of claim 12 , wherein the input pad is set to a floating state in the second phase of the test mode.

14. An apparatus comprising:
an input pad;
a first phase;
a first input buffer comprising a first input node and a second input node;
a first switch configured to couple the first input node and the second input node in an active state and further configured to decouple the first input node and the second input node in an inactive state;
a control circuit configured to provide a signal causing the first switch to be in the active state or an inactive state responsive to an inactive latch enable signal in the first phase of a test mode,
wherein the first input node is coupled to the input pad.

15. The apparatus of claim 14 ,
wherein the control circuit is configured to receive an enable signal, and
wherein the control circuit is configured to provide the signal causing the first switch to be in the active state responsive to an inactive state of the enable signal, and further configured to provide the signal causing the first switch to be in the inactive state responsive to an active state of the enable signal.

16. The apparatus of claim 15 , further comprising a latch,
wherein the control circuit is configured to provide a latch enable signal causing the latch to receive an output signal from the first input buffer while the first switch is in the active state,
wherein the control circuit is configured to provide a latch timing signal responsive to the enable signal, and
wherein the latch is configured to latch the output signal from the first input buffer and further configured to provide the output signal to an output terminal responsive to the latch timing signal.

17. The apparatus of claim 16 , wherein the latch timing signal is activated substantially simultaneously when the first switch is switching from the active state to the inactive state.

18. The apparatus of claim 16 , wherein the control circuit is coupled to a memory cell array;
wherein the control circuit is configured to suspend access to the memory cell array responsive to the inactive state of the enable signal.

19. The apparatus of claim 15 , further comprising:
a second input buffer comprising a third input node and a fourth input node; and
a second switch configured to couple the input pad and the third input node in an active state and further configured to decouple the input pad and the third input node in an inactive state,
wherein the control circuit is configured to receive a first command from the first input buffer,
wherein the control circuit is configured to provide a first signal causing the second switch to be in the active state or in an inactive state, responsive to the first command indicative of a test command and further configured to provide a second signal causing the second input buffer to receive a second command responsive to the first command.

20. The apparatus of claim 19 , further comprising a selector,
wherein the control circuit is configured to provide a third signal causing the selector to select an input source from either the first input buffer or the second input buffer, and
wherein the selector is configured to selectively provide an output signal from either the first input buffer or the second input buffer, responsive to the third signal.

Assignees

• Micron Technology Inc

Inventors

• Okuma Sadayuki

Classifications

• G11C7/1087

  Data input latches · CPC title

• G11C7/1084 Primary

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C29/12015

  comprising clock generation or timing circuitry · CPC title

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C29/12005

  comprising voltage or current generators · CPC title